DBT-2005 :      IEEE INTERNATIONAL WORKSHOP on

CURRENT & DEFECT BASED TESTING

May 1, 2005     Lodge at Rancho Mirage, Palm Springs, CA, USA

Held in conjunction with      IEEE VLSI Test Symposium (VTS-05)

 

GENERAL CHAIR

Sankaran M. Menon

Intel Corporation, USA

CO-GENERAL CHAIR

Hans Manhaeve

Q-Star Test nv Brugge, Belgium

VICE-GENERAL CHAIR

Jim Plusquellic

Univ. of Maryland, Baltimore County

PROGRAM CHAIR

Mehdi Tahoori

Northeastern University, USA

LOCAL ARRANGEMENTS
P. Roy, Intel

FINANCE CHAIR
Sankaran M. Menon

Intel Corporation, USA

PUBLICITY CHAIR

Michel Renovell

LIRMM, France

ADVISOR

Charles Hawkins 

University of New Mexico, USA

PAST GENERAL CHAIR

Adit Singh

Auburn University, USA

STEERING COMMITTEE

Yashwant K. Malaiya (Chair)

                Colorado State University, USA

Anura  Jayasumana C ol State Univ, USA

Joan Figueras, UPC, Barcelona, Spain

Rochit Rajsuman, Advantest, USA

Kozo Kinoshita, Osaka University, Japan

PROGRAM COMMITTEE

Robert Aitken, Agilent Technologies,

Waleed Al-Assadi, IBM, USA

Tom Barnett, Auburn University, USA

Sreejit Chakravarty, Intel, USA

Anne Gattiker, IBM, USA

Sri Jandhyala, Texas Instruments, USA

Ali Keshavarzi, Intel, USA

Kozo Kinoshita, Osaka University, Japan

Bram Kruseman, Philips, The Netherlands

Peter Maxwell, Agilent Technologies,
Ed McCluskey, Stanford Univ., USA

Michel Renovell, LIRMM, France

Andrew Richardson, Lancaster Univ.,
Marly Roncken, Intel, USA

Rob Roy, Mobilian, USA

Manoj Sachdev, Univ. of Waterloo
Jaume Segura, UIB, Balears, Spain

Jerry Soden, Sandia National Labs, USA

Claude Thibeault,Ecole de Tech Sup,Canada

Duncan (Hank) Walker, Texas A&M Univ.

Victor Zieren, Philips Res., The Netherlands

CALL FOR PAPERS AND PARTICIPATION

Theme: Realizing Defect-Based Test in Production Test Flows

One of the fundamental questions in testing community is the effectiveness of defect-based testing approaches in the production test flow. Defect-based testing has the potential to better handle emerging defect types and changing circuit sensitivities in VDSM circuits compared to conventional stuck-at (structural) test.  Nevertheless, we need to better understand how many and which types of defects can be uniquely detected only by defect-based test techniques. However, some of the unique detections performed by defect-based testing can be just due to the lack of thorough structural test, such as untested faults or un-modeled faults. Data, experience, and lessons learned from test floor regarding the application of DBT in production test flow are essential to answer this question. Another issue is the problem of performing defect-based test in a foundry environment. This problem is pronounced for smaller companies in which appropriate information flow between the companies and their foundries is crucial for performing defect-based test.

The IEEE International Workshop on Current and Defect Based Testing (DBT 2005) is aimed at addressing these issues and others related to “Realizing Defect-Based Test in Production Test Flows”. Paper presentations on topics related to those given below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.

·         Delay Testing

·         Shorts, Bridges & Open Defects

·         IDDQ and IDDT Testing

·         Low voltage Testing

·         Elevated Voltage Testing & Stress Testing

·         Test Generation Tools

·         Reliability and Yield

·         Burn In Minimization

·         Noise and Cross-talk Testing

·         Nanometer Test Challenges

·         VDSM Defect Mechanisms

·         Technology Trends and Testing

·         IDDQ Limit Setting

·         Mixed Current/Voltage Testing

·         Economics of  Defect Based Testing

·         On and Off Chip Current Sensors

·         Defect Coverage & Metrics

·         Fault Localization & Diagnosis

To present at the workshop, submit a postscript or Acrobat (PDF) version of an extended abstract of at least 1000 words via E-mail to the Program Chair by Jan. 15, 2005. Each submission should include full name and address of each author, affiliation, telephone number, FAX and E-mail address. The presenter should also be identified. Camera-ready papers for distribution in the informal proceedings will be due on April 8, 2005. Presentations on cutting edge test technology, innovative test ideas, and industrial practices and experience are welcome.  Proposals for debates, panel discussions or “spot-light” presentations describing industrial experiences are also invited.

AUTHOR’S SCHEDULE:

                                Submission of Extended Abstract:                    Jan 15, 2005

                                Notification of Acceptance:                               Mar 25, 2005

                                Camera Ready Paper:                                           Apr 8, 2005

Technical Program Submissions:                   General Information

Mehdi Tahoori                                               Sankaran Menon

Electrical & Computer Engineering                                   Intel Corporation

Northeastern University                                                     1501 S. Mopac Expressway               

Boston, MA 02115, USA                                                    Austin, TX 78738, USA

Tel: (617) 373-2032, x-8970(FAX)                                       Tel: (512) 314-0573, x-0523(FAX)

E-mail: mtahoori@ece.neu.edu                         E-mail: Sankaran.Menon@intel.com

Visit our www site at: http://www.cs.colostate.edu/~malaiya/dbt.html

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Sponsored by: IEEE Computer Society Test Technology Technical Committee