library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity SVGA_sync is

  generic (
    Row_Wid : integer := 10;            -- How many Bits for the Row
    Col_Wid : integer := 10;            -- How many bits for the Col
    VTdisp  : integer := 600;           -- Vert Display Time (In Lines)
    VTpw    : integer := 6;             -- Vert Pulse Width (In Lines)
    VTfp    : integer := 37;            -- Vert Front Porch (In Lines)
    VTbp    : integer := 23;            -- Vert Back Porch (In Lines)
    HTdisp  : integer := 800;           -- Horiz Display Time (In Clocks)
    HTpw    : integer := 120;           -- Horiz Pulse Width (In Clocks)
    HTfp    : integer := 56;            -- Horiz Front Porch (In Clocks)
    HTbp    : integer := 64);           -- Horiz Back Porch (In Clocks)

  port (
    Clk     : in  std_logic;            -- Pixel Clock
    Rst     : in  std_logic;
    HSync   : out std_logic;
    VSync   : out std_logic;
    Refresh : out std_logic;
    Row     : out std_logic_vector(Row_Wid-1 downto 0);
    Col     : out std_logic_vector(Col_Wid-1 downto 0);
    Enable  : out std_logic);

end SVGA_sync;

architecture Behavior of SVGA_sync is

  constant HPulseStart  : integer := HTdisp + HTbp;
  constant VPulseStart  : integer := VTdisp + VTbp;
  constant HPulseEnd    : integer := HTdisp + HTbp + HTpw;
  constant VPulseEnd    : integer := VTdisp + VTbp + VTpw;
  constant HTs          : integer := HTdisp + HTpw + HTfp + HTbp;
  constant VTs          : integer := VTdisp + VTpw + VTfp + VTbp;
  signal   HCount       : integer range 0 to HTs-1;
  signal   VCount       : integer range 0 to VTs-1;
  signal   Next_HCount  : integer range 0 to HTs-1;
  signal   Next_VCount  : integer range 0 to VTs-1;
  signal   Next_Refresh : std_logic;
  signal   Next_Enable  : std_logic;
  signal   Next_HSync   : std_logic;
  signal   Next_VSync   : std_logic;

begin

  Col <= std_logic_vector(to_unsigned(HCount, Col_Wid));
  Row <= std_logic_vector(to_unsigned(VCount, Row_Wid));

  MakeNextCount : process (HCount, VCount)
  begin
    if HCount = HTs -1 then
      Next_HCount <= 0;
      if VCount = VTs -1 then
        Next_VCount <= 0;
      else
        Next_VCount <= VCount + 1;
      end if;
    else
      Next_HCount <= HCount + 1;
      Next_VCount <= VCount;
    end if;
  end process MakeNextCount;

  Next_HSync   <= '1' when next_HCount >= HPulseStart and next_Hcount < HPulseEnd else '0';
  Next_VSync   <= '1' when next_VCount >= VPulseStart and next_Vcount < VPulseEnd else '0';
  Next_Enable  <= '1' when next_Hcount < HTdisp and next_Vcount < VTdisp          else '0';
  Next_Refresh <= '1' when next_Hcount = HTdisp and next_Vcount = VTdisp-1        else '0';
  
  Registers : process (Clk, Rst)
  begin
    if Rst = '1' then
      HCount  <= 0;
      VCount  <= 0;
      HSync   <= '1';
      VSync   <= '1';
      Enable  <= '1';
      Refresh <= '0';
    elsif Clk'event and Clk = '1' then
      HCount  <= Next_HCount;
      VCount  <= Next_VCount;
      HSync   <= Next_HSync;
      VSync   <= Next_VSync;
      Enable  <= Next_Enable;
      Refresh <= Next_Refresh;
    end if;
  end process Registers;
end Behavior;