library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity Top is
  
  port (
    Clk50MHz : in  std_logic;
    BTN0     : in  std_logic;
    RED      : out std_logic;
    GREEN    : out std_logic;
    BLUE     : out std_logic;
    HSYNC    : out std_logic;
    VSYNC    : out std_logic;
    LD0      : out std_logic);

end Top;

architecture Structure of Top is

  component SVGA_sync
    generic (
      Row_Wid : integer;
      Col_Wid : integer;
      VTdisp  : integer;
      VTpw    : integer;
      VTfp    : integer;
      VTbp    : integer;
      HTdisp  : integer;
      HTpw    : integer;
      HTfp    : integer;
      HTbp    : integer);
    port (
      Clk     : in  std_logic;
      Rst     : in  std_logic;
      HSync   : out std_logic;
      VSync   : out std_logic;
      Refresh : out std_logic;
      Row     : out std_logic_vector(Row_Wid-1 downto 0);
      Col     : out std_logic_vector(Col_Wid-1 downto 0);
      Enable  : out std_logic);
  end component;
  
  signal Reset : std_logic;
  signal Clock : std_logic;

  signal Next_Red   : std_logic;
  signal Next_Green : std_logic;
  signal Next_Blue  : std_logic;
  signal Next_HSync : std_logic;
  signal Next_VSync : std_logic;
  
  signal Row        : std_logic_vector(9 downto 0);
  signal Col        : std_logic_vector(9 downto 0);
  signal EnableI    : std_logic;
  -- signal Refresh : std_logic;

begin

  Reset <= BTN0;
  Clock <= Clk50MHz;
  SVGA_sync_1 : SVGA_sync
    generic map (
      Row_Wid => 10,
      Col_Wid => 10,
      VTdisp  => 600,
      VTpw    => 6,
      VTfp    => 37,
      VTbp    => 23,
      HTdisp  => 800,
      HTpw    => 120,
      HTfp    => 56,
      HTbp    => 64)
    port map (
      Clk     => Clock,
      Rst     => Reset,
      HSync   => Next_HSync,
      VSync   => Next_VSync,
      Refresh => open,
      Row     => Row,
      Col     => Col,
      Enable  => EnableI);

  -- purpose: register process
  -- type   : sequential
  -- inputs : Clock, Reset
  -- outputs: 
  MakeReg: process (Clock, Reset)
  begin
    if Reset = '1' then
      HSync <= '0';
      VSync <= '0';
      Red   <= '0';
      Green <= '0';
      Blue  <= '0';
    elsif Clock'event and Clock = '1' then
      HSync <= Next_HSync;
      VSync <= Next_VSync;
      Red   <= Next_Red;
      Green <= Next_Green;
      Blue  <= Next_Blue;
    end if;
  end process MakeReg;
  
  Next_Red   <= EnableI;
  Next_Green <= Col(5) when EnableI = '1' else '0';
  Next_Blue  <= Row(5) when  EnableI = '1' else '0';
  LD0 <= EnableI;
end Structure;