library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity counter is

  generic (
    WIDTH : integer := 8);
  port (
    Clock     : in  std_logic;
    Reset     : in  std_logic;
    Increment : in  std_logic;
    Value     : out std_logic_vector(WIDTH-1 downto 0));

end counter;

architecture behavior of counter is

  signal count      : unsigned(WIDTH-1 downto 0);  -- output of register
  signal next_count : unsigned(WIDTH-1 downto 0);  -- input of register

begin

  next_count <= count + 1;

  MakeReg : process (Clock, Reset)
  begin
    if Reset = '1' then
      count <= (others => '0');
    elsif Clock'event and Clock = '1' then
      if(Increment = '1') then
        count <= next_count;
      end if;
    end if;
  end process MakeReg;

  Value <= std_logic_vector(count);

end behavior;