library IEEE;
use IEEE.std_logic_1164.all;

entity dff is
  
  port (
    Rst : in  std_logic;
    Clk : in  std_logic;
    D   : in  std_logic;
    Q   : out std_logic);

end dff;

architecture behavior of dff is

begin
-- purpose: d flipflop
-- type   : sequential
-- inputs : Clk, Rst, D
-- outputs: Q
fliflo: process (Clk, Rst)
begin
  if Rst = '1' then
    Q <= '0';
  elsif Clk'event and Clk = '1' then
    Q <= D;
  end if;
end process fliflo;

end behavior;