library IEEE;
use IEEE.std_logic_1164.all;

entity dreg is

  generic (
    bitwidth : integer := 4);
  port (
    Rst : in  std_logic;
    Clk : in  std_logic;
    D   : in  std_logic_vector(bitwidth-1 downto 0);
    Q   : out std_logic_vector(bitwidth-1 downto 0));

end dreg;

architecture behavior of dreg is

begin

  -- purpose: register
  -- type   : sequential
  -- inputs : Clk, Rst
  -- outputs: q
  regit: process (Clk, Rst)
  begin
    if Rst = '1' then
      Q <= (others => '0');      
    elsif Clk'event and Clk = '1' then
      Q <= D;
    end if;
  end process regit;

end behavior;