library ieee;
use ieee.std_logic_1164.all;

entity shift_register is
  
  generic (
    WIDTH : integer := 8);

  port (
    Clock    : in  std_logic;
    Reset    : in  std_logic;
    Shift_It : in  std_logic;
    Val      : in  std_logic_vector(WIDTH-1 downto 0);
    Val_D1   : out std_logic_vector(WIDTH-1 downto 0);
    Val_D2   : out std_logic_vector(WIDTH-1 downto 0);
    Val_D3   : out std_logic_vector(WIDTH-1 downto 0);
    Val_D4   : out std_logic_vector(WIDTH-1 downto 0));

end shift_register;

architecture behavior of shift_register is

  -- Why do I need these?
  signal My_Val_D1 : std_logic_vector(WIDTH-1 downto 0);
  signal My_Val_D2 : std_logic_vector(WIDTH-1 downto 0);
  signal My_Val_D3 : std_logic_vector(WIDTH-1 downto 0);
  signal My_Val_D4 : std_logic_vector(WIDTH-1 downto 0);
  
begin

  MakeRegs : process (Clock, Reset)
  begin
    if Reset = '1' then
      My_Val_D1 <= (others => '0');
      My_Val_D2 <= (others => '0');
      My_Val_D3 <= (others => '0');
      My_Val_D4 <= (others => '0');
    elsif Clock'event and Clock = '1' then
      if(Shift_It = '1') then
        -- Does the order matter here? (Trick Question!)
        My_Val_D1 <= Val;
        My_Val_D2 <= My_Val_D1;
        My_Val_D3 <= My_Val_D2;
        My_Val_D4 <= My_Val_D3;
      end if;
    end if;
  end process MakeRegs;
  
  Val_D1 <= My_Val_D1;
  Val_D2 <= My_Val_D2;
  Val_D3 <= My_Val_D3;
  Val_D4 <= My_Val_D4;

end behavior;