library ieee;
use ieee.std_logic_1164.all;

entity shift_register is
  
  generic (
    WIDTH : integer := 8;
    DEPTH : integer := 3);

  port (
    Clock    : in  std_logic;
    Reset    : in  std_logic;
    Shift_It : in  std_logic;
    Val_In   : in  std_logic_vector(WIDTH-1 downto 0);
    Val_Out  : out std_logic_vector((WIDTH * DEPTH)-1 downto 0));

end shift_register;

architecture behavior of shift_register is

  -- Why do I need these?
  signal My_Val_Out : std_logic_vector((WIDTH * DEPTH)-1 downto 0);
  
begin

  MakeRegs : process (Clock, Reset)
  begin
    if Reset = '1' then
      My_Val_Out <= (others => '0');
    elsif Clock'event and Clock = '1' then
      if(Shift_It = '1') then

        My_Val_Out(WIDTH-1 downto 0) <= Val_In;

        My_Val_Out((WIDTH * DEPTH)-1 downto WIDTH) <=
          My_Val_Out((WIDTH * (DEPTH-1))-1 downto 0);

      end if;
    end if;
  end process MakeRegs;
  
  Val_Out <= My_Val_Out;

end behavior;