Title: SPARTA: A Dataflow-Inspired System Design

Abstract:
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Computer systems have undergone a fundamental transformation recently,
from single-core processors to devices with increasingly higher core
counts within a single chip. The semi-conductor industry now faces the
infamous power and utilization walls. To meet these challenges,
heterogeneity in design, both at the architecture and technology
levels, will be the prevailing approach for energy efficient computing
as specialized cores, accelerators, etc., can eliminate the energy
overheads of general-purpose homogeneous cores. However, with future
technological challenges pointing in the direction of on-chip
heterogeneity, and because of the traditional difficulty of parallel
programming, it becomes imperative to produce new system software
stacks that can take advantage of the heterogeneous hardware. As a
case in point, the core count per chip continues to increase
dramatically while the available on-chip memory per core is only
getting marginally bigger. Thus, data locality, already a must-have in
high-performance computing, will become even more critical as memory
technology progresses. In turn, this makes it crucial that new
execution models be developed to better exploit the trends of future
heterogeneous computing in many-core chips. To solve these issues, we
propose a cross-cutting cross-layer approach to address the challenges
posed by future heterogeneous many-core chips.