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BMAC Fall 2007: Abstracts


Software Reliability and Security Engineering
Dr. Yashwant Malaiya
Colorado State Univesity


Abstract
There are several factors that control software reliability and security. This talk examines the quantitative approaches that are needed to achieve desired reliability targets. There is now sufficient quantitative data available that can be used to develop and validate the models that describe the key processes. The reliability measure which are generally used are defined. The factors that impact defect density and defect finding rates will be examined and software reliability growth modeling will be presented. Both test-time and test-coverage based models will be introduced. Modeling for security vulnerabilities will also be presented. Reliability of multi-component software systems will be discussed followed by optimal allocation of test resources to achieve a target reliability level.

BIO

Yashwant K. Malaiya is a Professor in Computer Science Department at Colorado State University. He has published widely in the areas of security vulnerabilities, fault modeling, software and hardware reliability, testing and testable design. He served as General Chair of IEEE International Symposium on Software Reliability Engineering (ISSRE), Denver, 2003; IEEE Asian Test Symposium (ATS), Shanghai, 1999; General Chair, Sixth International Conference on VLSI Design (VLSI Design '93), Bombay, India, 1993. He has co-edited the IEEECS Tech. Series books ``Software Reliability Models, Theoretical Developments, Evaluation and Applications'' and ``Bridging Faults and IDDQ Testing''. He was a guest editor of special issues of IEEE Software and IEEE Design & Test. He received the IEEE Third Millennium Medal, 2000 and IEEE CS Golden Core Award, June 1996 for services to IEEE Computer Society


Challenges for Consumer Electronics in the 21st Century
Steve Leibson
Tensilica, Inc.


Abstract
The era of perpetual and nomadic connection to information and entertainment sources is upon us. Wireless and wired connections rain audio, video, and data into every conceivable type of consumer device, ranging from mobile telephone handsets to PDAs to cameras, camcorders, media players, and video games. Omnipresent video screens appear in your home, in airports, in bars, and even at individual tables in restaurants and gasoline pumps. The future belongs to a broad spectrum of connected devices delivering myriad combinations of sound, image, video, and data over a wide range of channels with varied bandwidths. The major challenges in delivering these new consumer products involve the development of smart, adaptable, low-power systems that can deliver high-quality user experiences while compensating for the imperfections of peripheral components such as inexpensive lenses, less-than-ideal display technologies, and tiny sound drivers. Moore's Law has laid a transistor bounty at the feet of every system architect but the systems being designed today continue to suffer from self-inflicted bottlenecks. The industry seeks ways to fully exploit those billions of on-chip transistors; there is a vast opportunity to develop new system architectures and system-design methodologies that can fully exploit this bounty of Moore's Law.

BIO

Steven Leibson is the Technology Evangelist for Tensilica, Inc. He formerly served as the Vice President of Content and Editor in Chief of the Microprocessor Report, Editor in Chief of EDN Magazine, and Founding Editor in Chief of Embedded Developers Journal magazine. He has conducted many seminars and tutorials on system design around the world, has written hundreds of articles that appeared in many of the world’s industry trade magazines, and has won many industry awards for his writing. He published the book 'Designing SOCs with Configured Cores' in 2006, which discusses the concepts of IP-driven and processor-centric SOC design for the 21st century. This book advocates across-the-board advances in system design, leaving behind antiquated ASIC design styles that are now almost two decades old. Leibson received his degree from Case Western Reserve University and worked in industry as a design engineer and engineering manager for leading-edge system-design companies including as Hewlett-Packard and Cadnetix. Leibson is an IEEE Senior Member.


Power-Aware High-Performance Computing: The Dawn of a New Era
Ishfaq Ahmad
Computer Science and Eng Dept
University of Texas at Arlington

Abstract
Energy is one of the most valuable and scarce resources, a major portion of which is now being consumed to power up computers and their accessories. We address several research issues in power-aware computing at various levels, such as system, software, and applications. Power-awareness is an essentially important issue in pervasive environments due to battery constraints. We focus on video compression, which due to its intensive computational requirements can quickly deplete a battery. The theoretical basis of current video compression technologies is the quintessential R-D (rate-distortion) model that epitomizes the non-linear relationship between distortion and target bit rate. The model allows a video encoder to allocate bits to the compressed video so as to minimize the predicted distortion function given a bit rate constraint--the higher the bit rate, the lower the distortion, and vice versa. In this talk, we introduce a new paradigm of video encoding to develop "smart" (for the lack of a better word) but highly efficient video encoders. We propose a theoretical P-R-D (power-rate-distortion) model that facilitates the understanding of the interactions as well as tradeoffs between power, bit rate, distortion, and complexity. In other words, the model enables an encoder to relate distortion to bit rate as well as power, where the latter is mapped to the encoding complexity. This in turn allows the encoder to apply optimization techniques for preserving the power while enhancing its visual quality. A software-based architecture is also proposed that allows the proposed techniques to be used in conjunction with MPEG and H.26X video coding standards.

BIO

Dr. Ishfaq Ahmad (http://ranger.uta.edu/~iahmad/) received a B.Sc. degree in Electrical Engineering from the University of Engineering and Technology, Pakistan, in 1985, and an MS degree in Computer Engineering and a PhD degree in Computer Science from Syracuse University, New York, U.S.A., in 1987 and 1992, respectively. He is currently a professor of Computer Science and Engineering at the University of Texas at Arlington (UTA). Prior to joining UT Arlington, he was on the faculty of the Computer Science Department of Hong Kong University of Science and Technology (HKUST). At HKUST, he also directed the Multimedia Technology Research Center, a university-wide research center that he conceived and established with other colleagues. At UTA, he leads the Multimedia Laboratory and Institute for Research in Security (IRIS). IRIS, an inter-disciplinary research center spanning several departments, is engaged in research on futuristic technologies for homeland security and law enforcement. Professor Ahmad is known for his research contributions in parallel and distributed computing, grid computing, multimedia computing, video compression, and security. His work in these areas is published in close to 200 technical papers in peer-reviewed journals and conferences, including three best paper awards at leading conferences and 2007 best paper award for IEEE Transactions on Circuits and Systems for Video Technology. His current research is funded by the Department of Justice (DOJ), National Science Foundation (NSF), and industry. He is an associate editor of the Journal of Parallel and Distributed Computing, IEEE Transactions on Circuits and Systems for Video Technology, IEEE Transactions on Multimedia, IEEE Distributed Systems Online, and Cluster Computing.



Don Towsley
University of Massachusetts

The Internet is Flat: A Brief History of Networking in the Next Ten Years

Abstract
The current Internet consists of ten to twenty thousand different interconnected autonomous networks. In many cases these networks have negotiated cumbersome bilateral and multilateral agreements that constrain how data is allowed to flow from source to destination. For example, universities can communicate with each other through the Abilene network but must rely on other networks to communicate with non-academic entities such as Google. These agreements generally impose a loose hierarchy on the Internet with respect to the flow of data and information. The recent development of peer-to-peer file sharing technology, however, has the unintended developed effect of relaxing and voiding these agreements. This has resulted in a "flattening" of the Internet. In this talk we peer into a crystal ball and examine the implications that peer-to-peer (p2p) technology may have on the Internet over the next ten years. In particular, we examine the effects of p2p on economics for Internet service providers (ISPs), and the impact on how they manage and engineer their networks. We focus on one p2p technology, "swarming," as exemplified by BitTorrent, and examine how it will flatten the Internet by becoming the core of a new data transfer architecture over the next ten years. Last, we present a research agenda centered on swarm technology to make this happen.

BIO

Dr. Don Towsley holds a B.A. in Physics (1971) and a Ph.D. in Computer Science (1975) from University of Texas. He is currently a Distinguished Professor at the University of Massachusetts - Amherst in the Department of Computer Science. He has held visiting positions at IBM T.J. Watson Research Center, Yorktown Heights, NY; Laboratoire MASI, Paris, France; INRIA, Sophia-Antipolis, France; AT&T Labs - Research, Florham Park, NJ; and Microsoft Research Lab, Cambridge, UK. His research interests include networks and performance evaluation. He currently serves as Editor-in-Chief of IEEE/ACM Transactions on Networking, and on the editorial boards of Journal of the ACM and IEEE Journal on Selected Areas in Communications, and has previously served on numerous other editorial boards. He was Program Co-chair of the joint ACM SIGMETRICS and PERFORMANCE '92 conference and the Performance 2002 conference. He is a member of ACM and ORSA, and Chair of IFIP Working Group 7.3. He has received the 2007 IEEE Koji Kobayashi Award, the 2007 ACM SIGMETRICS Achievement Award, the 1998 IEEE Communications Society William Bennett Best Paper Award, and numerous conference/workshop best paper awards. Last, he has been elected Fellow of both the ACM and IEEE.



Jose Moreira
IBM

Scale-up and Scale-out: Evolution and Trends in Parallel Processing

Abstract
An active research area since the 60s, parallel processing became mainstream in the information technology industry in the 90s. First, symmetric multiprocessors, or scale-up systems, with increasing number of processors became popular. More recently, clusters of interconnected machines, or scale-out systems, are the backbone of new important applications such as search engines and electronic markets. In this talk, we review the evolution and characteristics of these two types of systems. We identify their strengths and weaknesses and also the pain points associated with using them. We discuss new ideas that seek to combine the best of both worlds and present some preliminary results on that front. Finally, we discuss what are the business and innovation opportunities that can lead to new kinds of systems, such as the Blue Gene supercomputer.

Jose E. Moreira received B.S. degrees in physics and electrical engineering in 1987 and an M.S. degree in electrical engineering in 1990, all from the University of Sao Paulo, Brazil. He received his Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign in 1995. Since joining IBM in 1995, he has been involved in several high-performance computing projects, including the Teraflop-scale ASCI Blue-Pacific, ASCI White, and Blue Gene/L. Jose was the System Software Architect for Blue Gene/L, a project in which he worked for the last 6 years. Starting February 1st, Jose took a new job as Chief Architect of the new Commercial Scale Out initiative at IBM Research.



James Du
North Dakota State University

A Routing-Driven Key Management Scheme for Heterogeneous Sensor Networks

Abstract
Previous research on sensor network security mainly considers homogeneous sensor networks, where all sensor nodes have the same capabilities. Research has shown that homogeneous ad hoc networks have poor performance and scalability. The many-to-one traffic pattern dominates in sensor networks, and hence a sensor may only communicate with a small portion of its neighbors. Key management is a fundamental security operation. Most existing key management schemes try to establish shared keys for all pairs of neighbor sensors, no matter whether these nodes communicate with each other or not, and this causes large overhead. In this paper, we adopt a Heterogeneous Sensor Network (HSN) model for better performance and security. We propose a novel routing-driven key management scheme, which only establishes shared keys for neighbor sensors that communicate with each other. We utilize Elliptic Curve Cryptography in the design of an efficient key management scheme for sensor nodes. The performance evaluation and security analysis show that our key management scheme can provide better security with significant reductions on communication overhead, storage space and energy consumption than other key management schemes.

BIO

Xiaojiang (James) Du is an Assistant Professor in the Department of Computer Science at North Dakota State University. Dr. Du received his B.E. degree from Tsinghua University, Beijing, China in 1996, and his M.S. and Ph.D. degrees from University of Maryland, College Park in 2002 and 2003, respectively, all in Electrical Engineering. His research interests are heterogeneous wireless sensor networks, security, wireless networks, computer networks, network and systems management, and controls. Dr. Du has published over 50 journal and conference papers in the above areas. Dr. Du's research is supported by the NSF (National Science Foundation), Army Research Office, and NASA (National Aeronautics and Space Administration). He is an Associate Editor of four international journals: Wireless Communication and Mobile Computing (Wiley), Security and Communication Networks (Wiley), Journal of Computer Systems, Networking, and Communications (Hindawi) and International Journal of Sensor Networks (InderScience). Dr. Du is (was) the Chair of Computer and Network Security Symposium of the ACM International Wireless Communication and Mobile Computing Conference 2008, 2007 and 2006. He is (was) a Technical Program Committee member of several major IEEE conferences such as INFOCOM, ICC, GLOBECOM, WCNC, IM, NOMS, BroadNet, and IPCCC.



John Michalakes
NCAR, MMM Division, Boulder

High Performance Computing and Atmospheric Modeling

Abstract
Atmospheric modeling, one of the first high performance applications, remains a cycle-hungry domain today as we move to petascale computing. Designed from the outset for HPC, the Weather Research and Forecast (WRF) - widely used for operational weather forecasting, hurricane prediction, regional climate simulation, atmospheric chemistry, and basic atmospheric research -- is now exploiting systems comprising tens of thousands of cores as well as non-traditional architectures using Graphics Processing Units and the Cell processor. This talk presents a look back and a look forward at HPC and numerical weather prediction as a scientific computing challenge.

BIO

John Michalakes is a senior software engineer in the Mesoscale and Microscale Meteorology division of the National Center for Atmospheric Research in Boulder, Colorado and is lead software developer for the Weather Research and Forecast (WRF) model. He received the UCAR Outstanding Technical Achievement Award in 2004 for this work. Prior to NCAR, he was a computer scientist in the Mathematics and Computer Science division at Argonne National Laboratory. He holds a masters degree in computer science from Kent State University (1988) and is currently working towards a PhD in the computer science program at the University of Colorado in Boulder.



Mike Flynn
Stanford University


Super SOC: Putting the Whole System on the Chip

Abstract
With dramatic advances in transistor density, it's time to look ahead to the completely autonomous system on a single die (ASOC). This represents a convergence of RFID type technology with SOC silicon technology coupled with silicon transducers, sensor controllers and battery, all on the same die. The major architectural implication is design for extremely low power (1 microwatt or less) and strict energy budget. This requires a rethinking of clocking, memory organization, and processor organization. The use of deposited thin film batteries, extremely efficient RF, digital sensors and MEMS (micro-electro-mechanical systems) complete the ASOC plan.

BIO

Michael Flynn began his engineering career at IBM as a designer of mainframe computers. He became Professor of Electrical Engineering at Stanford in 1975 where he set up the Stanford Architecture and Arithmetic group. He retired from Stanford in 1999. Some of his best-known work includes the development of the now familiar stream outline of computer organization (SIMD, etc.). For more than 30 years this has served as the fundamental formal taxonomy of parallel computers. In 1970 he co-authored the first detailed discussion of techniques for the simultaneous execution of multiple instructions, now called super scalar design. He is a Fellow of the ACM and a Fellow of the IEEE.



David H. Bailey
Lawrence Berkeley Laboratory


Experimental Mathematics and High-Performance Computing

Abstract
The field of high-performance computing has been very successful in enabling an ever-growing number of important scientific applications to be performed on high-end computer systems. Hardware advances, algorithm improvements, parallelization techniques, performance tools and visualization have all played a part. Recently this technology has been applied in novel ways to research problems in mathematics and mathematical physics. In particular, high-precision numerical computations using the "PSLQ" integer relation algorithm, in many instances implemented on highly parallel computer systems, have been used to discover new mathematical formulas and identities not previously known in the literature. One notable example was the discovery a few years ago of a new formula for pi, which has the remarkable property that it permits one to directly calculate binary or hexadecimal digits beginning at an arbitrary starting position. Many other results have recently been found in this manner, particularly in the area of mathematical physics. This talk gives a brief overview of the techniques used and some of the recent results.

BIO

David H. Bailey is a mathematician and computer scientist. He received his B.S. in mathematics from Brigham Young University in 1972 and his Ph.D. in mathematics from Stanford University in 1976. He worked for 14 years as a computer scientist at NASA Ames Research Center, but since 1998 has been the Chief Technologist of the Computational Research Department at the Lawrence Berkeley National Laboratory. Bailey is known as a co-author (with Peter Borwein and Simon Plouffe) of a 1996 paper that presented a new formula for pi. This Bailey-Borwein-Plouffe formula permits one to calculate binary or hexadecimal digits of pi beginning at an arbitrary position, by means of a simple algorithm. The formula was discovered by Simon Plouffe using a computer program written by Bailey. More recently (2001 and 2002), Bailey and Richard Crandall showed that the existence of this and similar formulas has implications for the long-standing question of "normality" - whether and why the digits of certain mathematical constants (including pi) appear "random" in a particular sense. Bailey also does research in numerical analysis and parallel computing. He has published studies on the fast Fourier transform, high-precision arithmetic, and the PSLQ algorithm (used for integer relation detection). He is a co-author of the NAS Benchmarks, which are used to assess and analyze the performance of parallel scientific computers. Bailey is a recipient of the Sidney Fernbach award from the IEEE Computer Society, as well as the Chauvenet Prize and the Hasse Prize from the Mathematical Association of America. Bailey and Jonathan Borwein are co-authors of two books on experimental mathematics.