Field Programmable Gate Arrays


An introduction

Field programmable gate arrays were invented in the mid-1980s as devices that resembled Application Specific Integrated Circuits (ASICs) but could be programmed after the chip was manufactured. They have become a well-established (currently $2billion per year) market since then. An FPGA consists of a matrix of programmable logic cells, with a grid of interconnecting lines and switches between them. I/O cells exist around the perimeter, providing an interface between the interconnect lines and the chip's external pins. The exact functionality of a logic cell varies with the manufacturer of the chip, but it is typically comprised of a small amount of functional logic and/or some register store capability. Programming (configuring) an FPGA consists of specifying the logic function of each cell and the switches in the interconnecting lines.

It is useful to relate an FPGA, used as a computing device, to a conventional RISC microprocessor. At a low level, both consist of gates that implement boolean logic. The conventional processor uses its logic to implement a fixed instruction set, in which each instruction has been chosen based on its usefulness to compilers in generating code for general purpose computing. The instructions are very simple, and performance is achieved by devising ways in which they can be rapidly loaded and executed.

The (re)configurability of an FPGA makes it possible to depart from the idea of a fixed instruction set. Instead, application-specific "instructions" can be specified, and these instructions can be orders of magnitude more complex than those found in RISC processors. The instructions can make heavy use of both breadth-wise and pipeline parallelism. The tradeoff is in the load time of the instruction. Whereas a RISC instruction on a conventional processor can load in a few nanoseconds, the load time of an FPGA instruction can be measured in milliseconds. This makes FPGAs suitable only for parts of applications that are highly regular and work on large data sets. Andre DeHon (1996) defines "computational density" as the number of bit operations a device can perform per unit of area-time, and calculates that ``reconfigurable architectures provide roughly an order of magnitude higher raw computational density than the programmable architectures.''

Virtually all FPGAs presently are programmed using one of the various hardware description languages, such as VHDL (VHSIC Hardware Description Language), or directly with logic circuit diagrams. In such low-level programming, where signal timing and synchronization issues must be dealt with explicitly, code development can be slow and tedious. Furthermore, some useful optimizations, such as loop unrolling, must be performed explicitly by the programmer, making it difficult to explore implementation alternatives. The goal of the Cameron project is to make it easier to exploit FPGAs as computing devices by allowing them to programmed in a more traditional, algorithmic (as opposed to circuit-based) language.