CS270 Colorado State University ========================== Sequential Circuits Review ========================== ------------------------ 2-bit saturation counter From PA2 writeup: "A 2-bit saturation counter starts at the count of 0. If a branch statement jumps, the count goes to 1. If a branch statement falls through, the count stays at 0. When the count is in state 1, a jump causes the count to go to 2, and a fall through causes the count to go to 0. In general, the count saturates at 0 when the count is going down and it also saturates at 3 when the count is going up. The output of the 2-bit saturation counter is to predict jump if the counter value is 2 or 3 and to predict fall through otherwise." Current Input Next State JUMP State OUT ------------------------------------------------------------ 0 B1=0,B0=0 0 0 B1=0,B0=0 0 (no jump) 0 B1=0,B0=0 1 1 B1=0,B0=1 0 (no jump) 1 B1=0,B0=1 0 0 B1=0,B0=0 0 (no jump) 1 B1=0,B0=1 1 2 B1=1,B0=0 1 (jump) 2 B1=1,B0=0 0 2 B1=1,B0=0 1 3 B1=1,B0=1 0 3 B1=1,B0=1 1 --------------------------- Exercises for midterm study minterm - A conjunction (AND) where each input variable appears once as itself or its inverse. 1. Given the following truth table (a) write the sum-of-products formula for the output. Make sure that the products are each a minterm. (b) Draw the circuit that directly corresponds to the formula. In other words, each operation in the formulat should correspond to a gate in the circuit. A B C OUT ------------------- 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 2. Given the following truth table (a) write the sum-of-products formula for the output. Make sure that the products are each a minterm. (b) Draw the circuit that directly corresponds to the formula. In other words, each operation in the formulat should correspond to a gate in the circuit. A B C OUT ------------------- 0 0 0 0 0 0 1 0 0 1 0 1 0 1 1 1 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 ----------- JMP example Format for JMP opcode 0 00 BaseR 000000 1100 0 00 111 000000 x3000 1100 0000 1100 0000 x3001 JMP R1 x3002 JMP R7 x3003 1100 0000 0100 0000 x3004 1100 0001 0000 0000 ... x4000 JMP R7 ------------------------- Cycle 1: all the gory details and the data path Fetch: MAR <- PC PC <- PC+1 MDR <- Mem IR <- MDR Decode: What is opcode and what does it stand for? what fields does opcode indicate are in instruction? Eval Address Nothing Fetch Operands Get value from R3. Execute A = BaseR = R3, B = SEXT(IR) ALUout = A + B Store Result PC = ALUout ------------------------- Cycle 2: just look at how register values change Fetch: MAR <- PC PC <- PC+1 MDR <- Mem IR <- MDR Decode: opcode = , BaseR = Fetch, Execute, Store PC = R3 ------------------------- Cycle 3: just look at how register values change Fetch: MAR <- PC PC <- PC+1 MDR <- Mem IR <- MDR Decode: opcode = , BaseR = Fetch, Execute, Store PC = R7 ------------------------- Cycle 4: just look at how register values change Fetch: MAR <- PC PC <- PC+1 MDR <- Mem IR <- MDR Decode: opcode = , BaseR = Fetch, Execute, Store PC = R1 ------------------------- Cycle 5: just look at how register values change Fetch: MAR <- PC PC <- PC+1 MDR <- Mem IR <- MDR Decode: opcode = , BaseR = Fetch, Execute, Store PC = R3 ------------------------- Cycles 6 and up ... ============= LC3 ISA ============= Chapter 5 ------------------------------ Goal questions for the LC3 ISA (1) Given the chart from the back cover of the book, decode and encode all of the LC3 instructions covered in Chapter 5. (2) How many registers and operations are there in the LC3 ISA? How do those numbers affect the instruction design? (3) What is an addressing mode? (4) What addressing modes does the LC3 ISA include and what are the semantics of each of the modes? (5) What are condition codes and how do they work in LC3? (6) Given a full datapath, highlight and describe the parts of the datapath used by individual LC3 instructions. (7) How can we implement an infinite and a finite loop in LC3? ------------------- Memory Load Example problem 5.23 in book What is the value in R2 at the end of executing the following program? x30FF 1110 0010 0000 0001 x3100 0110 0100 0100 0010 x3101 1111 0000 0010 0101 x3102 0001 0100 0100 0001 x3103 0001 0100 1000 0010 ------------------------- Cycle 1: all the gory details and the data path Fetch: MAR <- PC PC <- PC+1 MDR <- Mem IR <- MDR Decode: Eval Address Nothing Fetch Operands Get values from PC and instruction. Execute A = PC = x3100, B = SEXT(IR) ALUout = A + B Store Result DR = ALUout ------------------------- Cycle 2: all the gory details and the data path Fetch: MAR <- PC PC <- PC+1 MDR <- Mem IR <- MDR Decode: Eval Address BaseR is added to sext(offset6) Result is put into MAR. Fetch Operands Value is read from memory. Execute Nothing Store Result DR = MDR ------------------------- Cycle 3: some details and the data path Fetch: MAR <- PC PC <- PC+1 MDR <- Mem IR <- MDR Decode: Exercises for midterm study: 1) What happens during each phase of the instruction cycle for LD, ST, LDI, and STI? 2) What is in the datapath for LD, ST, LDI, and STI? ---------------- Addressing Modes Addressing mode indicates where the operand is located. 1. Register 2. Immediate 3. Memory The effective address is encoded in instruction (direct or PC-relative). Pointer to effective address is encoded in instruction (indirect) Pointer to the effective address is in a register. (relative, or base+offset) ------------------------ mstrout@cs.colostate.edu, 9/24/08