CS270 Colorado State University

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I/O
=============

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I/O
    Input / Output
    
        

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I/O interface for LC3: Keyboard and Monitor Registers

    KBDR
        
    
    
    KBSR
        
    
        keyboard flag set means character is available
    
    
    
    DDR
        
    
    
    DSR
        
    
        monitor flag set means character has been displayed
    
    
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Memory Mapped I/O

    Map device registers to memory location
        KBSR --> xFE00
        KBDR --> xFE02
        DSR  --> xFE04
        DDR  --> xFE06
    
    Access device registers with loads and stores to those memory locations.
    
    
    Benefits
        Use existing instructions instead of needing new instructions.
        

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Synchronous Input

    Synchronization is the coordination of events to operate a system in
unison. (wikipedia)
    
    Events to synchronize
        
        
        
        

    (Similar to exercise 8.3 in book)
    How fast would a person have to type (in words per minute) 
    to supply characters to the CPU at the
    maximum rate the CPU can process the characters?
    
        clock rate 2.0 GHz
        
        processor executes one instruction at a time
        
        one instruction takes 100 clock cycles to execute
        
        assume an average word length of 6
        
        
        
        
      
        
        
        
        
        
        
        
        
        
        
         
        
                                       

    Typist is not fast enough to keep up with CPU and cannot be expected to 
    perform at a specific rate.


    The interactions between CPU and keyboard, CPU and display device,
    CPU and disk, etc. are all asynchronous and therefore need some form
    of synchronization.
    

---------------------------
Polling vs. Interupt Driven

    
    
    Polling (CPU is in control of synchronization)
        
        
        
        Input
            1) CPU checks KBSR in a loop
            
            
            
            
            2) keyboard cannot accept input while KBSR is set
            
            3) CPU loads KBDR value into register
            
            
            
            3b) When KBDR is read, the keyboard logic clears
            the KBSR.

            4) Keyboard can accept input when KBSR is clear.

        Example that shows why immediate clearing of KBSR is necessary.
        
            
            
            
    
    
        Output
            1) CPU checks DSR in a loop
             
            
            
            
            2) CPU writes character to DDR
            
            
            
            2b) Monitor logic clears DSR when DDR is written.
            
            
            3) Monitor sets DSR after it has displayed character.
            
            
        Study Question:
            What could happen if the CPU was responsible
            for clearing the DSR with a store instruction?
    
    
    
    Interrupt-Driven I/O
        Synchronization is controlled by I/O device.
        
        I/O device makes service request.
            
            
        If the device has high enough priority, then 
            1) CPU stops what it is doing, 
            
            2) handles the request, and
            
            3) continues where it left off


        Interrupt signal is conjunction/AND of bits 15 and 14
        in the KBSR and DSR.  Bit 14 is set if interrupts are 
        enabled.
        
        Processor checks for interrupts in the STORE RESULT
        phase, therefore possibly changing what instruction
        is fetched next.


    Performance comparison (Example 8.1 in book)
    
        
    
    
    
    
    
    
    
    
    
    
    
    
    Study questions
        Exercise 8.7 in book
        
        Exercise 8.9 in book
        
        Exercise 8.11 in book


--------------------------------------------
Memory Mapped I/O Implementation in Hardware
Read C.5 in book

    
    
    MAR - Memory Address Register
    
    MIO.EN - Is the current instruction a memory load or store?
    
    R/W - Read if have a load instruction, Write if have a store
    
    MEM.EN - if set enables reads and writes from memory
    
    IN.MUX - selects amongst data being loaded from KBDR, KBSR, DSR, or memory
    
    LD.KBSR, LD.DSR, LD.DDR - indicates whether the various registers should
        be set to their input value
    
    
    MAR     MIO.EN  R.W     MEM.EN  IN.MUX  LD.KBSR LD.DSR  LD.DDR
    ---------------------------------------------------------------
    xFE00   1       W       
    xFE00   1       R       
    
    xFE06   1       W       
    xFE06   1       R       
    
    other   1       W       
    other   1       R       
    
    


    Study Questions (Ch 8 and C.5)
        Which of the device registers in LC3 can be written to by CPU?
            
            
        Which of the device registers can be read by CPU?

        Assume we are in an architecture with 32-bit words.  If all addresses
        with their first 8 bits set to one are set aside as device register
        addresses, how many memory locations are there for device registers 
        and for the rest of memory?



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mstrout@cs.colostate.edu, 10/22/08