Project Navigator Tutorial
Project Navigator will allow you to create a project, include your VHDL files, synthesize your VHDL code, translate, map, and place and route your circuit for the FPGA specified in the project. Next, Project Navigator will generate the files to be down loaded onto the FPGA. Finally, Project Navigator will start iMPACT to download your bitmap file onto the FPGA. For this tutorial, we will build a parity checker.
The Tutorial - Quick Steps
The Tutorial - Detailed Steps
Double click the Project Navigator ICON on the desktop. When Project Navigator starts, its GUI will be displayed which will include four window panes.
i. Click File on the menu bar and select "New Project..."
ii. In the New Project dialog box:
1. Enter a project name.
2. Make sure the Project Location is the directory you wish to contain your project.
3. Leave the Top-Level Module Type as HDL.
4. Click the Next button.
5. Verify the Properties are set as follows:
Device Family: Spartan3
Speed Grade: -4
Top-Level Module Type: HDL
Synthesis Tool: XST (VHDL/Verilog)
Generated Simulation Language: VHDL
Click Next if the properties are correct. Otherwise, correct the properties and then click next.
6. Click Next again (no changes to Create a New Source)
7. Click Next again (no changes to Add Existing Sources)
8. Review the project specification to make sure they are correct and then click Finish.
NOTE: The UCF file maps signals in your VHDL code to pins on the Spartan3 board. The new UCF file you created has all lines commented out. Uncomment just the signals you are actually using. It is extremely important to uncomment just the lines you are using. If you uncomment lines you are not using, you may introduce unexplained behavior.
For the UCF file to map a pin on the Digilent board to a signal in your top.vhd file, the signal name in your .vhd file must match the net name in the UCF file. If the names do not match, change the name in your .vhd file, not the net name in the .UCF file. The software tools you are using run on both Unix and Windows systems. Unix implementation are case sensitive. In general, Windows implementation of these tools do not maintain the case sensitivity. However, every now and then you may come across a feature in the tools that still enforces case sensitivity on a Windows platform. For this reason, it is recommended that you strive to keep signal names consistent in your .vhd and .ucf files.
a. For each input signal in top.vhd, uncomment the associated line in top.ucf.
b. For each output signal in top.vhd, uncomment the associated line in top.ucf.
NOTE: Comments in .ucf files begin with the # character.
i. Make sure your project folder is selected.
ii. Select one of your vhd files and then click the open button.
iii. A Choose Source Type dialog box will appear.
iv. Select VHDL Design File (if not already selected) and click OK.
v. Repeat for each of the .VHD files you need to include into the project.
vi. Include your .UCF file. When prompted, be sure to associate your .ucf file with top.vhd.
Note: At this,or an earlier, point, it would be wise to create a
.do file and model your VHDL code.
This will simplify debugging.
Click in top left pane on top-mixed (TOP.VHD)
This will walk through all the steps required to implement your design. If you prefer, you can double click each phase individually.
Resolve any errors and repeat step 5C until the project completes with no errors.
In step 5C, by double clicking "Configure Device (iMPACT)", iMPACT will start automatically. When Impact starts, it will display a series of dialog boxes.
i. Make sure the correct directory is selected in the Look In: edit box.
ii. Select the top.bit file
iii. Click the open button.
i. In the popup menu, select "Program..."
The "Program Options" dialog box will appear.
ii. Click the OK button.
A progress bar will appear while the file is being down loaded.
iii. The bitmap generated by your VHDL code is now loaded on the Digilent board.