Lab 1(a)
Full Adder

For the first part of your first lab, all you need to do is add bits together! Okay, It isnt quite that simple, but that is the general idea. You are given a vhdl component for a HalfAdder and a ModelSim do file which tests the HalfAdder. You must create a vhdl entity/architecture for a FullAdder, which uses Two HalfAdders as components.

HalfAdder diagram (We give you this and a test script)

HalfAdder.vhd and

FullAdder diagram (You make and test this)

To get an A for this half you should:

Lab 1(b)

For the second part of this lab you will learn to add small numbers. You will start with the FullAdder you made in part A. You must create a vhdl entity/architecture for a RippleCarryAdder, which uses multiple FullAdders as components. Your RippleCarryAdder should have one generic, named Size, which specifies the width of the two inputs to the adder. The output should be 1 bit longer than the inputs, to prevent overflow. For example, if Size is set to 8, the inputs A and B should both be 8 bits long, and S should be 9 bits. The default for Size should be 4, but please test it with other sizes as well.

Example 5-bit Ripple Carry Adder

To get an A for this part, you should: