For the first part of your first lab, all you need to do is add bits together!
Okay, It isnt quite that simple, but that is the general
idea. You are given a vhdl component for a HalfAdder
and a ModelSim do file which tests the
HalfAdder. You must create a vhdl entity/architecture for a FullAdder, which
uses Two HalfAdders as components.
HalfAdder diagram (We give you this and a test script)
Show us your FullAdder.vhd -- Containing the entity/architecture pair for your FullAdder entity/architecture.
Show us your FullAdder.do -- For convincing us that your component works correctly.
Show us that your full adder works correctly for every combination of inputs.
Your full adder should fit the circuit diagram shown above, and use the same port names.
Your .do file should test every possible combintion of inputs to the full adder.
Both the VHDL file and the test file should be easy to read, understand, grade, etc.. You should comment the files where needed and use reasonable identifiers.
Convince us that you understand what you have done, and be prepared to answer questions about it.
For the second part of this lab you will learn to add small numbers. You will
start with the FullAdder you made in part A. You must create a vhdl
entity/architecture for a RippleCarryAdder, which uses multiple FullAdders as
components. Your RippleCarryAdder should have one generic, named Size,
which specifies the width of the two inputs to the adder. The output should be
1 bit longer than the inputs, to prevent overflow. For example, if Size
is set to 8, the inputs A and B should both be 8 bits long, and
S should be 9 bits. The default for Size should be 4, but please test
it with other sizes as well.
Example 5-bit Ripple Carry Adder
To get an A for this part, you should:
Show us your RippleCarryAdder.vhd -- Containing the entity/architecture pair for your RippleCarryAdder entity/architecture.
Show us your RippleCarryAdder.do for convincing us that your adder works correctly.
Your adder should work correctly. (S = A + B)
Your full adder should fit the circuit diagram shown above (if I were to set Size to 5), using the same port names.
Your .do file should test several (5 or more) combinations of inputs,
including checking for overflow conditions.
Both the VHDL file and the do file should be easy to read, understand, grade, etc.. You should comment the files where needed and use reasonable identifiers.