Your job is to create an accumulator using your Ripple-Cary-Adder that you
created in lab 1(b). Your adder will have two 7-bit inputs, with a 8 bit
result. Your Accumulator will consist of a register used for storing the sum,
and your Ripple-Cary-Adder to perform the addition. Each rising clock edge,
the binary value present on the input will be added to the register.
For example, when the system starts (or after the Reset has been asserted),
the register should contain all 0s. If you then set the input value to
"0000101", the register will increment by 5 every time a clock event arrives.
Notice that we do not supply you with a diagram to work from. This does NOT
mean that you dont need one. You should CAREFULY draw a diagram of each
component in your design (and part b)! Think about the behavior of the design
before you begin writing it in VHDL! If you ask for help, we will probably
ask to see your diagram first! We also want you to think about what will
happen when an overflow occurs.
For the second half, you will put your accumulator onto the Spartan3 Board and
make it sing and dance! The first button on the board (BTN0) will be debounced, and
used as your Clock. The second button (BTN1) will be used to reset the
accumulator and the debouncer. Seven switches will be your binary input
(SW6-SW0), and the Leds (LD7-LD0) will show the result. For the Leds and
Switches, #0 represents the low order bit. This way, the binary values will
have their MSB on the left, and the LSB on the right, just as you would
Accumulator on the Spartan3 Board
For the debouncer, you should use the on-board clock (Clk50Mhz) and debounce
for 16K to 32K clock cycles (You may want to expirement with the length of the
debouncer to see how it effects the chip utilization and behavior of the final
You should test each VHDL component in Modelsim before going to hardware.
Your entire project (A&B) should consist of the following files:
You must show us all your VHDL code, UCF file, do files etc... and be prepared
to answer questions about them, and explain why you did what you did.
- Top.vhd -- Top level entity which instantiates your debouncer and your
accumulator. The signal names of the portmap of top should
match the ones in the UCF file.
- Accum.vhd -- The actual accumulator which instantiates your Ripple Cary
Adder, and contains the state register(s).
- DeBounce.vhd -- The Debouncer component used to debounce BTN0 so that it
can be used as a clock.
- RippleCaryAdder.vhd -- Your Ripple Carry Adder from Lab 1b
- FullAdder.vhd -- Your Full Adder from Lab 1a
- HalfAdder.vhd -- The Half Adder we gave you from Lab 1a
- Spartan3.ucf -- The UCF file for your system. Be sure to include ALL of
the required signals in your design, and to comment out
- DeBounce.do -- Modelsim Test script for testing the DeBouncer.
- Accum.do -- Modelsim Test script for testing the Accumulator.
- Top.do -- Modelsim Test script for testing the Top Level Entity.