Homework Assignment

CS 470: Computer Architecture

Spring 2004

Note:  The written assignments are due at the beginning of the class.

· HW Set 1: Due Tuesday, Feb. 10,

Appendix b:

B.4

B.8

B.15

B.16

B.17 Minimize the PLA.

B.24 Minimize the PLA

Additional: Redraw diagram B.16 if the D flipflop is rising edge-triggered

· HW2: Due Thursday Feb 19

Using MMLogic (http://www.softronix.com/logic.html), implement a full adder using and/or/not gates. Supply inputs using switches and monitor output using LEDs.

Submit your logic file (.lgi) using webct (to be set-up soon).

· HW3: Due Thursday Feb 26

2.13 [There may be an error in Exercise 2.13 on page 92 in older editions of the text. The table entry for row c, column 3 (“CPI on M2”) should be 3 instead of 8.]

2.18

2.31

2.44

· HW4: Due Tuesday April 6

3.3, 3.5, 3.24

4.5, 4.9, 4.17

Implement the fig. 4.17 (Top only) using MMLogic. Verify your implementation. Submit the printout.

Multiply 0101 by multiplier 0110 using a table like Fig 4.33.

· Program 2: Due Thursday April 8

Implement the program as specified in problem 3.26. Submit using Webct.

· HW5: Due Thursday May 6

5.1 (Hint: Answers should be like this: if RegDst=0, all R-format instructions will not work properly because we will specify the wrong register to write. )

5.5 (Hint: no additions to data-path are required, you should know why. )

5.6 (Hint: expansion of a couple of multiplexers may be needed)

5.14 (Hint: the lw instruction is providing the longest path of length 8 ns).

5.15 (Hint: existing datapath is sufficiant. Adding a new state may be required).

5.16 (Hint: Dispatch ROMs may need to be changed.)