Review Sheet for Final

Note: On this Friday, I will be availalable during 1:30-2:30 PM.

Please also see review sheets for Test 1 and Test 2

IEEE Floating point representation 
Conversions (p. 279-280)
Normalized and denormalized (p. 300) numbers
Floating point addition (p. 282) and multiplication.

Instruction fetch and execution data paths
One-cycle design: Info flow in the data path
r-type, lw/sw, beq, j instructions
Control signals and control design
Worst-case delays and maximum clock frequency

Multicycle design
Data path and control signals
Instruction implementations
RTL descriptions (fig 5.35) and state diagram
Control design: FSM (p. c-19) and microprogrammed (sec. C.4