CS 551: Distributed Operating Systems
Types of Consistency
Types of Consistency
- There are many different models of consistency,
some of which are included in the list below:
- Strict Consistency Model:
"The strict consistency model is the strongest form
of memory coherence, having the most stringent consistency
requirements. A shared-memory system is said to support
the strict consistency model if the value returned by a read
operation on a memory address is always the same as the value
written by the most recent write operation to that address,
irrespective of the locations of the processes performing
the read and write operations. That is, all writes
instantaneously become visible to all processes."
- Sequential Consistency Model:
"The sequential consistency model was proposed by
Lamport ... . A shared-memory system is said to support
the sequential consistency model if all processes see the
same order of all memory access operations on the shared
memory. The exact order in which the memory access
operations are interleaved does not matter. ... If one process
sees one of the orderings of ... three operations and another
process sees a different one, the memory is not a sequentially
- Casual Consistency Model:
"The causal consistency model ... relaxes the
requirement of the sequential model for better concurrency.
Unlike the sequential consistency model, in the causal
consistency model, all processes see only those memory
reference operations in the same (correct) order that
are potentially causally related. Memory reference operations
that are not potentially causally related may be seen by
different processes in different orders."
- FIFO Consistency Model:
For FIFO consistency, "Writes done by a single
process are seen by all other processes in the order in
which they were issued, but writes from different processes may
be seen in a different order by different processes.
"FIFO consistency is called PRAM consistency in the case of
distributed shared memory systems."
- Pipelined Random-Access Memory (PRAM)
"The pipelined random-access memory (PRAM) consistency
model ... provides a weaker consistency semantics than
the (first three) consistency models described so far.
It only ensures that all write operations performed by a
single process are seen by all other processes in the order
in which they were performed as if all the write operations
performed by a single process are in a pipeline. Write
operations performed by different processes may be seen
by different processes in different orders."
- Weak Consistency Model:
"Synchronization accesses (accesses required to perform
synchronization operations) are sequentially consistent.
Before a synchronization access can be performed, all previous
regular data accesses must be completed. Before a regular
data access can be performed, all previous synchronization
accesses must be completed. This essentially leaves the
problem of consistency up to the programmer. The memory
will only be consistent immediately after a synchronization
- Release Consistency Model:
"Release consistency is essentially the same as weak
consistency, but synchronization accesses must only be
processor consistent with respect to each other.
Synchronization operations are broken down into acquire
and release operations. All pending acquires (e.g.,
a lock operation) must be done before a release (e.g., an
unlock operation) is done. Local dependencies within the same
processor must still be respected.
"Release consistency is a further relaxation of weak
consistency without a significant loss of coherence."
- Entry Consistency Model:
"Like ... variants of release consistency, it requires the
programmer (or compiler) to use acquire and release at the
start and end of each critical section, respectively.
However, unlike release consistency, entry consistency
requires each ordinary shared data item to be associated
with some synchronization variable, such as a lock or
barrier. If it is desired that elements of an array be
accessed independently in parallel, then different array
elements must be associated with different locks. When an
acquire is done on a synchronization variable, only those
data guarded by that synchronization variable are made
- Processor Consistency Model:
"Writes issued by a processor are observed in the same order
in which they were issued. However, the order in which writes
from two processors occur, as observed by themselves or a
third processor, need not be identical. That is, two
simultaneous reads of the same location from different
processors may yield different results."
- General Consistency Model:
"A system supports general consistency if all the copies
of a memory location eventually contain the same data when all
the writes issued by every processor have completed."
- Also see the table on p. 316 of (Tanvan02)
Copyright © 2001-2003:
Colorado State University for CS 551.
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