CS553 Colorado State University ========================================== Register allocation ========================================== 9/15/09 ------------------------- Decision Tree for Register allocation (slide 2) Scope Expr Local Loop Global Granularity Variable Live ranges/Webs Values Weighting units of allocation Profile ld/st counts Static approx (8.8.2) in book, usage and liveness ... Approach Graph coloring: assumes an interference graph is built Use weights to do greedy assignment of registers to alloc units -Have temp registers and spill when needed or redraw interference graph when need to spill Simplification approaches: Chaitin and Briggs Interprocedural ------------------------- Simplification Approaches (slide 3) Renumber - renumbering the allocation units, In Briggs paper the allocation unit is a live range. We will focus on variables as the allocation unit. Build - building interference graph Virtual register being defined interferes with all liveout virtual registers. Coalesce - merge allocation units Can merge variables involved in a copy that do not interfere otherwise. Have to merger their interference edges as well. Spill costs - weighting on each allocation unit Simplify - put nodes that know can color on a stack, in increasing order of importance? Spill code - if need to spill temps then modify code and start over Select - assign colors/registers to allocation units ----------------------------- Chaitin Allocator (slides 5-7) Why start over after spilling? When we insert spill code, we are removing one symbolic register/temporary and inserting two. The new temporaries have short live ranges. The problem with Chaitin's algorithm is that it pessimistically spills because it assumes that all neighbors for a node will have different colors. ----------------------------- Briggs Allocator, Optimistic Spilling (slides 8-10) Key idea is to push temporary onto the stack even if it might not be colorable. ----------------------------- Coalescing (slides 11-13) --> for example in slide 12 create interference graph ----------------------------- Spilling (slides 14-16) -could keep 2-3 registers aside to avoid recreation of the interference graph -there are many ways to compute the weights of each symbolic register/temporary ----------------------------- Register allocation and procedure calls (slide 17) The main problem is that the procedure being called (the callee) might modify registers that are live across the call. Calling convention: what assumptions can be made about registers across calls ----------------------------- Calling convention (slide 18) A lot of things affect calling convention design. We are going to assume the design is set and show how an interference register allocator can deal with it. ----------------------------- Caller and Callee Saved (slides 19-21) Part of the calling convention is what registers the caller and callee are responsible for saving. ----------------------------- Register Allocation and Calling Conventions (slide 22) -conservative approach is to always save and restore caller registers around a function call and always save and restore callee registers in function prologues and epilogues ----------------------------- Precolored Nodes (slide 23-25) - can't spill callee-saved or caller-saved registers - could make it so that temps can only allocate from caller-saved, but what if have something that is live across call, need to have ability to "spill" callee-saved registers and/or caller registers ----------------------------- Tradeoffs between callee-saved and caller-saved registers (slide 26-27) ----------------------------- Suggested Exercises - how do we know we won't end up in an infinite loop where we are always spilling the same register?