Project Suggestions

This page is still under construction

Remember, these are merely suggestions, and you are more than welcome to propose something on your own. Most projects are fairly open ended, and therefore could be suitable for one or two students. It is not desirable to have more than one "group" (i.e., one or two students together) working on the same project: the idea is not to be in competition but to work synergistically on different aspects of the problem. So the following list is available "for grabs" on a first-come first-served basis. It would also be nice if the groups inolved students with complementary skills (eg. one ECE and one CS student). There are essentially three types of projects.

Applications

Tools

These projects concern the development of "compilation" tools for mapping Alpha programs to VHDL (in the context of this class, we will use FPGA based co-processor boards as our target).

Tiling

Tiling is a loop transformation that has a number of objectives: improving the communication to computation ratio in loop programs on general-purpose parallel machines, optimizing the performance of codes on (sequential or parallel) machines with a well defined memory hierarchy, etc. It is also used in partitioning systolic arrays for implementation on bounded resources. Thus, many issues that arise in tiling for general purpose machines are of interest to us (even though not all of them specifically involve silicon compilation, the objectives of CS670). Moreover, since the techniques used are very similar, I nevertheless list all potential tiling projects here.