State University   CS 670 DV, Spring 2003

Architectures of Advanced Systems:

Embedded & Reconfigurable Systems

Class meets: Tu-Th 16:50 - 18:10 in USC 310B




Sanjay Rajopadhye,
Phone: (970) 491-7323
Office: 223 University Services
Office Hours: to be announced


Course Overview:

Keywords: Systolic Arrays, FPGAs, Loop Parallelization, Silicon Compilation, Systems-on-a-Chip, Codesign.

This class (co-listed as ECE670) is a special topics advanced graduate class, (previously offered in Fall 2001). It deals with the foundations of high performance, parallel embedded and reconfigurable systems. Specifically, we will study how to design highly parallel, special purpose architectures (called systolic arrays) for compute/data intensive loop programs. We will implement them on FPGA based reconfigurable co-processors. We will also study how these arrays may be designed automatically: the issues involved in compiling programs directly to silicon.

Prerequisites: You should have taken at least two of CS-570/EE-554 (Computer Architecture), EE-571 (VLSI System Design), CS-553 (Compilers) and CS-575 (Parallel Processing). You should have very high mathematical maturity (especially in linear algebra, and optimization): you don't have to know all the math beforehand, but you should not be afraid to pick it up if needed. Please come and see me if you have questions.

Being a CS-ECE cross-listed course, I hope that we can synergistically build on the the strengths and backgrounds of all students. Although CS670 is a variable credit course, this one is for 4 credit-hrs (you may register for less but you will have to do the same work :-) [top]

Textbooks and References:

There is no required text. We will usually work off papers in the literature and lecture notes. In addition, the following is a set of useful references [top]

Tentative Schedule:

There will be five modules of about 3-weeks each, covering the following topics. [top]

Grading Policy:

You grade will be determined by a combination of homeworks (30%), a take-home midterm (30%) and a final project (40%). You will need to plan the project early, submit intermediate and final reports and make a final in-class presentation.