Class activities will be recorded here.

This page has the entire plan for the semester. For weeks in the future, consider it a plan subject to change. For weeks in the past consider it a record of what we have done. As for the current week, keep a watch for updates and changes.

• Day	Topics	Milestone

Week 1 : August 25 - August 31

• Tuesday	Introduction and tentative reading list (pdf) A short recap by Tia Newhall on how to read and review papers How to read a paper, by S. Keshav Reading a computer science research paper, by Philip Fong
  Thursday	Scientific Grand Ghallenges: Crosscutting Technologies for Computing at the Exascale (pdf) read only the intro and pages 9-17; be prepared to discuss	HW0

Week 2 : September 1 - September 7

• Tuesday	Dark silicon and the end of multicore scaling, by Esmaeilzaeh et al Authors: Esmaeilzadeh, Blem, St. Amat, Sankaralingam, and Burger, ISCA 2011
  Thursday	Debunking the 100X GPU vs. CPU Myth: an Evaluation of Throughput Computing on CPU and GPU Authors: Lee, Kim, Chhugani, Deisher, Kim, Ngyuen, Satish, Smelyanskiy, Chennupati, Hammarlund, Singhal, and Dubey, ISCA 2010

Week 3 : September 8 - September 14

• Tuesday	What to Do About the End of Moore's Law, Probably! Authors: Palem, and Lingamneni, ACM/IEEE DAC 2012
  Thursday	Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver, by Zhang et al. Authors Zhang, Betz and Rose, ACM TRETS, March 2012 (Non Programable Accelerators)

Week 4 : September 15 - September 21

• Tuesday	Portable and Scalable FPGA-Based Acceleration of a Direct Linear System Solver, by Zhang et al. Authors Zhang, Betz and Rose, ACM TRETS, March 2012 (Non Programable Accelerators)	Project D1
  Thursday	Codesign tradeoffs for high-performance, low power linear algebra architectures, by Pedram et al Authors Pedram, van de Geijn, and Gerstlauer, IEEE Transactions on Computers, Dec 2012, (Non Programable Accelerators) Presented by Louis Rabiet

Week 5 : September 22 - September 28

• Tuesday	Writing a research proposal
  Thursday	No class, Sanjay traveling

Week 6 : September 29 - October 5

• Tuesday	No class, Sanjay traveling
  Thursday	Computer Generation of Hardware for Linear Digital Signal Processing Transforms, by Milder et al. Authors Milder, Fanchetti and Hoe, ACM TODAES, April 2012 (Non Programable Accelerators)	Project D2

Week 7 : October 6 - October 12

• Tuesday	Bridging the Computation Gap Between Programmable Processors and Hardwired Accelerators by Kevin Fan, Manjunath Kudlur, Ganesh Dasika and Scott Mahlke, in IEEE HPCA 2009 (Tradeoffs) Presented by Waruna Ranasinghe	MiniRE D1
  Thursday	Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators by Yunsup Lee, Rimas Avizienis, Alex Bishara, Richard Xia, Derek Lockhart, Christopher Batten, and Krste Asanovic, in ACM/IEEE ISCA 2011 (Tradeoffs)

Week 8 : October 13 - October 19

• Tuesday	A Hybrid and Adaptive Model for Predicting Register File and SRAM Power Using a Reference Design by Eric Donkoh, Alicia Lowery and Emily Shriver, in ACM/IEEE DAC 2012 (Memory Systems+Power)
  Thursday	A Case for Exploiting Subarray-Level Parallelism (SALP) in DRAM by Yoongu Kim, Vivek Seshadri, Donghyuk Lee, Jamie Liu and Onur Mutlu, in ACM/IEEE ISCA 2012 (Memory Systems)

Week 9 : October 20 - October 26

• Tuesday	The Hierarchical Multi-Bank DRAM: A High-Performance Architecture for Memory Integrated with Processors by Tadaaki Yamauchi, Lance Hammond, and Kunle Olukotun, in ARVLSI 1997: ACM Symposium on Advanced Research in VLSI (Memory Systems)	Project D3
  Thursday	Register Organization for Media Processing by Scott Rixner, William Dally, Brucek Khailany, Peter Mattson, Ujval Kapasi and John Owens, in ACM/IEEE HPCA 2000 (Memory Systems)

Week 10 : October 27 - November 2

• Tuesday	Optimizing Memory Hierarchy Allocation with Loop Transformations for High-Level Synthesis by Jason Cong, Peng Zhang, Yi Zou, in ACM/IEEE DAC, 2012 (HLS) Presented by Yun Zou	Project D4
  Thursday	Hierarchical Power Management for Adaptive Tightly-Coupled Processor Arrays by Vahid Lari, Shravan Muddasani, Srinivas Boppu, Frank Hannig, Moritz Schmidt and Jurgen Teich, in ACM TODAES, December 2012

Week 11 : November 3 - November 9

• Tuesday	Polyhedral Model based Mapping Optimization of Loop Nests for CGRAs by Dajiang Liu, Shouyi Yin, Leibo Liu, and Shaojun Wei, in ACM/IEEE DAC 2013
  Thursday	A High-Level Synthesis Flow for the Implementation of Iterative Stencil Loop Algorithms on FPGA Devices by Alessandro Nacci and Ivan Beretta, in ACM/IEEE DAC 2013 (HLS/Programmable Accelerators) Presented by Leon Durivage

Week 12 : November 10 - November 16

• Tuesday	Memory Partitioning for Multidimensional Arrays in High-level Synthesis by Yuxin Wang, Peng Li, Peng Zhang, Chen Zhang, and Jason Cong, in ACM/IEEE DAC 2013 (HLS) Presented by Rajbharath
  Thursday	A Compiler and Runtime for Heterogeneous Computing by Joshua Auerbach, David Bacon, Ioana Burcea, Perry Cheng, Stephen Fink, Rodric Rabbah and Sunil Shukla, in ACM/IEEE DAC 2012 Presented by Nirmal	MiniRE D2

Week 13 : November 17 - November 23

• Tuesday	Mini Research Exam Presentations	MiniRE D3
  Thursday	Mini Research Exam Presentations

Week 14 : November 24 - November 30

• Tuesday	Fall Break, no classes
  Thursday	Fall Break, no classes

Week 15 : December 1 - December 7

• Tuesday	Hybrid DRAM/PRAM-based Main Memory for Single-Chip CPU/GPU Dongki Kim, Sungkwang Lee, Jaewoong Chung, Dae Hyun Kim, Dong Hyuk Woo, Sungjoo Yoo andSunggu Lee, in ACM/IEEE DAC 2012
  Thursday	Decoupled DIMM: Building High-Bandwidth Memory System Using Low-Speed DRAM Devices by Hongzhong Zheng, Jiang Lin, Zhao Zhang, and Zhichun Zhu, in ACM/IEEE ISCA 2009 (Memory Systems)

Week 16 : December 8 - December 14

• Tuesday	To Be Determined.
  Thursday	Computation vs. Memory Systems: Pinning Down Accelerator Bottlenecks by Martha Kim and Stephen Edwards, in Workshops at ISCA 2010, selected papers, Springer Verlag	Project D5

Week :

• A Programmable Parallel Accelerator for Learning and Classification, by Cadambi et al. Authors Cadambi, Majumdar, Becchi, Chakradhar and Graf, PACT 2010, (Non Programable Accelerators)