Christopher D. Krieger

Graduate Student
Colorado State University
Computer Science Department
1873 Campus Delivery
Fort Collins, CO 80523-1873
krieger atsign cs dot colostate dot edu


 


Education

Graduate Student, Computer Science, Colorado State University, 2007 - present.
M.S., Electrical and Computer Engineering, University of Utah, 2002.
B.S., Electrical and Computer Engineering, Brigham Young University, 1995.

Research Interests

I'm now doing research in Computer Science at Colorado State. My advisor is Dr. Michelle Strout. From a high level, my research deals with finding ways to exploit the increasing number of hardware threads available from modern microprocessors to increase the performance of single-threaded applications.

I'm looking into programming models and language annotations, coupled with library based approaches. I think that an evolutionary approach, using existing languages supplemented with annotations or pragmas, backed by a library of support capabilities, joined together by compilers, will ultimately prove to be the most practical approach in the near term.

I've recently done research surrounding hardware data prefetchers. Many HPC scheduling algorithms, such as tiling, try to keep data accesses within a limited amount of memory. But these schedules often work counter to the data prefetching hardware on modern microprocessors. I am investigating the positive and negative interactions between hardware prefetching and tiling. I'll also propose different schedules that may garner maximum performance benefit through cooperation with the hardware prefetcher.

Previously, I've explored using virtual machines to dynamically detect parallelizable loops. I modified the Jikes RVM and gathered data on the potential this method has by testing a range of benchmarks, including NAS/JavaGrande and DaCapo.

My master's thesis research focused on asynchronous hardware systems. Specifically, I worked on efficient state coding of partially coded asynchronous systems, with performance of the final circuit as the driving cost function. This work could be extended to include concurrency reduction, particularly methods of altering system timing to remove state coding violations without completely removing concurrency.

Current Industry Work

I am currently working at Intel's Fort Collins Design Center on the Itanium® Processor Family (IPF) Performance Team. I am responsible for performance validation of the Poulson microprocessor. I also work on defining and using the Performance Monitoring Units found in Itanium® chips.

My previous work focused on improving timing convergence for microprocessor designs and automating chip-wide power reduction. I worked on two PA-RISC® processors (8700/8800), and 4 Itanium® processors. I ported many EDA tools to the IPF platform and evaluated compilers, tuning, and optimizations for large, irregular EDA applications on IPF.

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Coursework