VICE GENERAL Co-CHAIRs
Sankaran M. Menon
Q-Star Test nv
An important distinction between traditional stuck-fault testing and defect-based testing is the potential for the latter to better handle emerging defect types and changing circuit sensitivities in VDSM circuits. ITRS gives specific examples of emerging defects including the potential for more particle-related blocked-etch resistive opens that result from the change from a subtractive aluminum process to damascene Cu. A second example derives from aggressive scaling into the nanometer domain which increases the probability of incomplete etch and the occurrence of resistive vias. The testing challenges imposed by these types of resistive defects in combination with increased circuit sensitivity due to shorter clock cycles, reduced timing slack, crosstalk and PWR/GND bounce has elevated the level of interest and research into alternative, defect-based testing approaches.
The IEEE International Workshop on Current and Defect Based Testing (DBT 2004) is aimed at addressing these issues and others related to “VDSM Chips and the ‘Need’ for Defect Based Testing”. Paper presentations on topics related to those given below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.
The details of the technical program can be found at http://www.cs.colostate.edu/~malaiya/dbt2004program.html
Technical Program: General Information
Jim Plusquellic Adit Singh
Department of CSEE,
1000 Hilltop Circle 212 ECS,
Baltimore, MD 21250, USA Auburn, AL 36849, USA
Tel: (410) 455-1349, x-3969(FAX) Tel: (334) 844-1847, x-1809(FAX)
Visit our www site at: http://www.cs.colostate.edu/~malaiya/dbt.html