DBT-2004 :      IEEE INTERNATIONAL WORKSHOP on

CURRENT & DEFECT BASED TESTING

April 25, 2004  Napa Valley Marriott, Napa Valley, CA, USA

Held in conjunction with      IEEE VLSI Test Symposium (VTS-04)

 

GENERAL CHAIR

Adit Singh

Auburn University, USA

VICE GENERAL Co-CHAIRs

Sankaran M. Menon

Intel Corporation, USA

Hans Manhaeve

Q-Star Test nv Brugge, Belgium

PROGRAM CHAIR

Jim Plusquellic

Univ. of Maryland, Baltimore County

LOCAL ARRANGEMENTS
P. Roy

Intel,
USA

FINANCE CHAIR
Sankaran M. Menon

Intel Corporation, USA

PUBLICITY CHAIR

Michel Renovell

LIRMM, France

 

ADVISOR

Charles Hawkins 

University of New Mexico, USA

STEERING COMMITTEE

Yashwant K. Malaiya (Chair)

                Colorado State University, USA

Anura  Jayasumana C ol State Univ, USA

Joan Figueras, UPC, Barcelona, Spain

Rochit Rajsuman, Advantest, USA

Kozo Kinoshita, Osaka University, Japan

PROGRAM COMMITTEE

Robert Aitken, Agilent Technologies, USA

Waleed Al-Assadi, IBM, USA

Tom Barnett, Auburn University, USA

Sreejit Chakravarty, Intel, USA

Anne Gattiker, IBM, USA

Sri Jandhyala, Texas Instruments, USA

Ali Keshavarzi, Intel, USA

Kozo Kinoshita, Osaka University, Japan

Bram Kruseman, Philips, The Netherlands

Peter Maxwell, Agilent Technologies, USA
Ed McCluskey, Stanford Univ., USA

Michel Renovell, LIRMM, France

Andrew Richardson, Lancaster Univ., UK
Marly Roncken, Intel, USA

Rob Roy, Mobilian, USA

Manoj Sachdev, Univ. of Waterloo, Canada
Jaume Segura, UIB, Balears, Spain

Jerry Soden, Sandia National Labs, USA

Claude Thibeault,Ecole de Tech Sup,Canada

Duncan (Hank) Walker, Texas A&M Univ.

Victor Zieren, Philips Res., The Netherlands

An important distinction between traditional stuck-fault testing and defect-based testing is the potential for the latter to better handle emerging defect types and changing circuit sensitivities in VDSM circuits. ITRS gives specific examples of emerging defects including the potential for more particle-related blocked-etch resistive opens that result from the change from a subtractive aluminum process to damascene Cu.  A second example derives from aggressive scaling into the nanometer domain which increases the probability of incomplete etch and the occurrence of resistive vias.  The testing challenges imposed by these types of resistive defects in combination with increased circuit sensitivity due to shorter clock cycles, reduced timing slack, crosstalk and PWR/GND bounce has elevated the level of interest and research into alternative, defect-based testing approaches.  

 

 

The IEEE International Workshop on Current and Defect Based Testing (DBT 2004) is aimed at addressing these issues and others related to “VDSM Chips and the ‘Need’ for Defect Based Testing”. Paper presentations on topics related to those given below are expected to generate active discussion on the challenges that must be met to ensure high IC quality through the end of the decade.

 

 

The details of the technical program can be found at http://www.cs.colostate.edu/~malaiya/dbt2004program.html

 

 

 

 

 

 

Technical Program:                                        General Information

Jim Plusquellic                                               Adit Singh

Department of CSEE, Univ. of Maryland, BC     Dept. of Electrical Engineering

1000 Hilltop Circle 212 ECS,                              Auburn University        

Baltimore, MD 21250, USA                               Auburn, AL 36849, USA

Tel: (410) 455-1349, x-3969(FAX)                      Tel: (334) 844-1847, x-1809(FAX)

E-mail: plusquel@csee.umbc.edu                     E-mail: adsingh@eng.auburn.edu

Visit our www site at: http://www.cs.colostate.edu/~malaiya/dbt.html

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Sponsored by: IEEE Computer Society Test Technology Technical Committee