April 25, 2004  Napa Valley Marriott, Napa Valley, CA, USA

Held in conjunction with      IEEE VLSI Test Symposium (VTS-04)



Preliminary Program

7:30-8:30 Registration

8:30-8:45 Welcome & Program description
8:45-9:30 Keynote: Mike Tripp, Intel Corp.

9:30-10:00 coffee

10:00 - 11:20 IDDX methods and circuits (20 minutes each)
10:00 - 10:20
 Bin Xue and D.M.H. Walker, Built-in Current Sensor For IDDQ Test

10:20 - 10:40
Ali Chahab, Ayman Kayssi, Anis Nazer and Rafic Makki, "Improved Method for iDDT Testing in the Presence of Leakage and
Process Variation

10:40 - 11:00
Sagar Sabade and D.M.H. Walker, Comparison of Wafer-level Spatial IDDQ Estimation Methods: NNR
versus NCR

11:00 - 11:20
Dhruva Acharyya and Jim Plusquellic, Calibrating Power Supply Signal Measurements for Process and Probe  Card Variations

11:20 - 11:35 short break

11:35 - 12:00 Short presentations (10 minutes each)

11:35 - 11:45
Rich Ackerman,  "Doing More with Less: A Recipe for Rapid IDDQ Development
11:45 - 11:55
Hideo Kohinata, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, "Mixed Signal LSI Relationship among Measurement Accuracy, Yield, and Test Time

12:00-1:30 (lunch)

1:30-2:50 Delay Analysis (20 mins each)

1:30 - 1:50
Haihua Yan and Adit D. Singh, On the Effectiveness of Detecting Small Delay Defects in the Slack
1:50 - 2:10
 Claude Thibeault, On the Potential of Flush Delay for Characterization and Test  Optimization
2:10 - 2:30

Wangqi Qiu, Jing Wang and D.M.H. Walker, At-Speed Test for Path Delay Faults Using Practical Techniques

2:30 - 2:50
Bhushan Vaidya and Mehdi B. Tahoori,  Delay Testing Based on Transition Faults Propagated to All Reachable Outputs

2:50 - 3:10 short break

3:10 - 4:30 Speed Binning, Diagnosis and Bridging Defects (20 mins each)

3:10 - 3:30
Jing Zeng and Magdy Abadir,  On Correlating Structural Tests with Functional Tests for Speed
3:30 - 3:50
John Liobe and Martin Margala, Fault Diagnosis of a GHZ CMOS LNA Using High-Speed ADC-Based BIST

3:50 - 4:10
Piet Engelke, Ilia Polian, Michel Renovell and Bernd Becker, Automatic Test Pattern Generation for Resistive Bridging Faults

4:10 - 4:30 Short presentations (10 minutes each)

4:10 - 4:20
Rei-Fu Huang, Chin-Lung Su, Cheng-Wen Wu, Yeong-Jar Chang, and Wen-Ching Wu, A Memory Built-in Self-Diagnosis Design with Syndrome Compression
4:20 - 4:30
Maryam Ashouei, Abhijit Chattarjee and Adit Singh, A Test Data Compression Technique and Its Application to Scan

4:30-4:45 short break

4:45-6:00 Panel "ITRS test challenges need Defect-Based Test: fact or

The program committee for the Defect-Based Testing workshop has assembled a very strong program and welcomes attendees at VTS to register for Sundays all day event. Mike Trip from Intel will deliver the keynote address. The technical program consists of selected papers addressing important areas within Defect-Based Test including IDDX test, delay test, speed binning, diagnosis and bridging defects. A panel discussion rounds out the day that will debate the importance of Defect-Based Test for solving short-term and long-term ITRS test challenges.

To register for DBT-2004 workshop, visit VTS-2004 website (<http://www.tttc-vts.org/>http://www.tttc-vts.org/) and register for VTS / DBT-2004, or the registration form (in PDF format) is attached.   Deadline for advance registration is April 2nd, 2004.