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melange:papers:spring2017 [2017/01/24 15:33]
swetha 		melange:papers:spring2017 [2018/02/08 13:40] (current)
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 +@ARTICAL{123, author={Sanket Tavarageri, Albert Hartono, Muthu Baskaran, Louis-Noel Pouchet,J. Ramanujam
 +and P. Sadayappan}, title={Parametric Tiling of Affine Loop Nests}, year={2010}, doi = {http://web.cse.ohio-state.edu/~pouchet.2/doc/cpc-article.10.pdf} ,}
 +
 +
 +
 +
 +@INPROCEEDINGS{6043234, 
 +author={A. Pedram and A. Gerstlauer and R. A. v. d. Geijn}, 
 +booktitle={ASAP 2011 - 22nd IEEE International Conference on Application-specific Systems, Architectures and Processors}, 
 +title={A high-performance, low-power linear algebra core}, 
 +year={2011}, 
 +pages={35-42}, 
 +keywords={floating point arithmetic;matrix multiplication;GFLOPS-W;application-specific custom hardware;floating point operations per second;linear algebra core;matrix computations;matrix-matrix multiplication;power consumption reduction;technology scaling;Bandwidth;Computer architecture;Hardware;Kernel;Linear algebra;Program processors;Registers}, 
 +doi={10.1109/ASAP.2011.6043234}, 
 +ISSN={1063-6862}, 
 +month={Sept},}
 +
 +
 +
 +@inproceedings{Bandishti:2012:TSC:2388996.2389051,
 + author = {Bandishti, Vinayaka and Pananilath, Irshad and Bondhugula, Uday},
 + title = {Tiling Stencil Computations to Maximize Parallelism},
 + booktitle = {Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis},
 + series = {SC '12},
 + year = {2012},
 + isbn = {978-1-4673-0804-5},
 + location = {Salt Lake City, Utah},
 + pages = {40:1--40:11},
 + articleno = {40},
 + numpages = {11},
 + url = {http://dl.acm.org/citation.cfm?id=2388996.2389051},
 + acmid = {2389051},
 + publisher = {IEEE Computer Society Press},
 + address = {Los Alamitos, CA, USA},
 + keywords = {compilers, program transformation},
 +} 
 +
 +@ARTICLE{7582549, 
 +author={U. Bondhugula and V. Bandishti and I. Pananilath}, 
 +journal={IEEE Transactions on Parallel and Distributed Systems}, 
 +title={Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations}, 
 +year={2016}, 
 +url={http://ieeexplore.ieee.org/document/7582549/},
 +volume={PP}, 
 +number={99}, 
 +pages={1-1}, 
 +keywords={Diamond;Face;Indexes;Optimization;Parallel processing;Shape;Silicon;Compilers;locality;loop tiling;parallelism;program transformation;stencils}, 
 +doi={10.1109/TPDS.2016.2615094}, 
 +ISSN={1045-9219}, 
 +month={},}
 +
 +@ARTICLE{7155440, 
 +author={T. Nowatzki and J. Menon and C. H. Ho and K. Sankaralingam}, 
 +journal={IEEE Micro}, 
 +title={Architectural Simulators Considered Harmful}, 
 +year={2015},
 +url={http://ieeexplore.ieee.org/document/7155440/}, 
 +volume={35}, 
 +number={6}, 
 +pages={4-12}, 
 +keywords={computer architecture;digital simulation;architectural layers;architectural simulators;black boxes;evaluation standard recalibration;quantitative simulators;Analytical models;Benchmark testing;Computer architecture;Market research;Mathematical model;Simulation;architecture;benchmarks;evaluation standards;footprint;modeling;simulators;validation}, 
 +doi={10.1109/MM.2015.74}, 
 +ISSN={0272-1732}, 
 +month={Nov},}
 +
 +@INPROCEEDINGS{7349585, 
 +author={J. D. Garvey and T. S. Abdelrahman}, 
 +booktitle={2015 44th International Conference on Parallel Processing}, 
 +title={Automatic Performance Tuning of Stencil Computations on GPUs}, 
 +year={2015}, 
 +pages={300-309}, 
 +keywords={graphics processing units;learning (artificial intelligence);parallel processing;storage management;Nvidia GTX Titan GPU;OpenCL stencil kernel;automatic performance tuning;graphics processing unit;machine learning;optimization;random sampling;stencil computation;Graphics processing units;Instruction sets;Kernel;Merging;Optimization;Parallel processing;Yttrium;GPGPU;auto-tuning;machine learning;stencil}, 
 +doi={10.1109/ICPP.2015.39}, 
 +ISSN={0190-3918}, 
 +month={Sept},}
 +
 +@article{DBLPSteve,
 +  author    = {Sharan Chetlur and
 +               Cliff Woolley and
 +               Philippe Vandermersch and
 +               Jonathan Cohen and
 +               John Tran and
 +               Bryan Catanzaro and
 +               Evan Shelhamer},
 +  title     = {cuDNN: Efficient Primitives for Deep Learning},
 +  journal   = {CoRR},
 +  volume    = {abs/1410.0759},
 +  year      = {2014},
 +  url       = {http://arxiv.org/abs/1410.0759},
 +  timestamp = {Sun, 02 Nov 2014 11:25:59 +0100},
 +  biburl    = {http://dblp.uni-trier.de/rec/bib/journals/corr/ChetlurWVCTCS14},
 +  bibsource = {dblp computer science bibliography, http://dblp.org}
 +}
 +
 @article{Bao:2016:SDF:3012405.3011017, @article{Bao:2016:SDF:3012405.3011017,
- author = {Bao, Wenlei and Hong, Changwan and Chunduri, Sudheer and Krishnamoorthy, Sriram and Pouchet, Louis-No\"{e}l and Rastello, Fabrice and Sadayappan, P.},+ author = {Bao, Wenlei and Hong, Changwan and Chunduri, Sudheer and Krishnamoorthy, Sriram and Pouchet, Louis-Noel and Rastello, Fabrice and Sadayappan, P.},
  title = {Static and Dynamic Frequency Scaling on Multicore CPUs},  title = {Static and Dynamic Frequency Scaling on Multicore CPUs},
  journal = {ACM Trans. Archit. Code Optim.},  journal = {ACM Trans. Archit. Code Optim.},
Line 58: Line 152:
 }  } 
  
- 
- 
-@inproceedings{Kong:2013:PTM:2491956.2462187, 
- author = {Kong, Martin and Veras, Richard and Stock, Kevin and Franchetti, Franz and Pouchet, Louis-No\"{e}l and Sadayappan, P.}, 
- title = {When Polyhedral Transformations Meet SIMD Code Generation}, 
- booktitle = {Proceedings of the 34th ACM SIGPLAN Conference on Programming Language Design and Implementation}, 
- series = {PLDI '13}, 
- year = {2013}, 
- isbn = {978-1-4503-2014-6}, 
- location = {Seattle, Washington, USA}, 
- pages = {127--138}, 
- numpages = {12}, 
- url = {http://doi.acm.org/10.1145/2491956.2462187}, 
- doi = {10.1145/2491956.2462187}, 
- acmid = {2462187}, 
- publisher = {ACM}, 
- address = {New York, NY, USA}, 
- keywords = {affine scheduling, autotuning, compiler optimization, loop transformations, program synthesis}, 
-}  
 @article{cummins2017synthesizing, @article{cummins2017synthesizing,
  
Line 83: Line 158:
    author={Cummins, Chris and Petoumenos, Pavlos and Wang, Zheng and Leather, Hugh},    author={Cummins, Chris and Petoumenos, Pavlos and Wang, Zheng and Leather, Hugh},
  
-   year={2017}+   year={2017}, 
 +    
 +   url={http://homepages.inf.ed.ac.uk/hleather/publications/2017-benchsynth-cgo.pdf}
  
 } }
 +
 @article{optimistic2017, @article{optimistic2017,
  
Line 125: Line 203:
  
 [download] [download]
- 
-@article{Putnam:2014:RFA:2678373.2665678, 
- author = {Putnam, Andrew and Caulfield, Adrian M. and Chung, Eric S. and Chiou, Derek and Constantinides, Kypros and Demme, John and Esmaeilzadeh, Hadi and Fowers, Jeremy and Gopal, Gopi Prashanth and Gray, Jan and Haselman, Michael and Hauck, Scott and Heil, Stephen and Hormati, Amir and Kim, Joo-Young and Lanka, Sitaram and Larus, James and Peterson, Eric and Pope, Simon and Smith, Aaron and Thong, Jason and Xiao, Phillip Yi and Burger, Doug}, 
- title = {A Reconfigurable Fabric for Accelerating Large-scale Datacenter Services}, 
- journal = {SIGARCH Comput. Archit. News}, 
- issue_date = {June 2014}, 
- volume = {42}, 
- number = {3}, 
- month = jun, 
- year = {2014}, 
- issn = {0163-5964}, 
- pages = {13--24}, 
- numpages = {12}, 
- url = {http://doi.acm.org/10.1145/2678373.2665678}, 
- doi = {10.1145/2678373.2665678}, 
- acmid = {2665678}, 
- publisher = {ACM}, 
- address = {New York, NY, USA}, 
-}  
  
 @miscellaneous{accelerating-deep-convolutional-neural-networks-using-specialized-hardware, @miscellaneous{accelerating-deep-convolutional-neural-networks-using-specialized-hardware,
Line 250: Line 309:
   biburl    = {http://dblp.uni-trier.de/rec/bib/journals/corr/GruslysMDLG16},   biburl    = {http://dblp.uni-trier.de/rec/bib/journals/corr/GruslysMDLG16},
   bibsource = {dblp computer science bibliography, http://dblp.org}   bibsource = {dblp computer science bibliography, http://dblp.org}
 +}
 +
 +@inproceedings{FlowMap1994,
 + author = {J. Cong and Ding, Yuzheng},
 + title = {FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs},
 + booktitle = { IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
 + year = {1994},
 + isbn = {1937-4151},
 + pages = {1-12},
 + url = {http://ieeexplore.ieee.org/document/273754/},
 + doi = {10.1109/43.273754},
 + publisher = { IEEE}
 +} 
 +
 +@article{MILROY20161589,
 +title = "Towards Characterizing the Variability of Statistically Consistent Community Earth System Model Simulations",
 +journal = "Procedia Computer Science",
 +volume = "80",
 +number = "",
 +pages = "1589 - 1600",
 +year = "2016",
 +note = "",
 +issn = "1877-0509",
 +doi = "http://dx.doi.org/10.1016/j.procs.2016.05.489",
 +url = "http://www.sciencedirect.com/science/article/pii/S1877050916309759",
 +author = "Daniel J. Milroy and Allison H. Baker and Dorit M. Hammerling and John M. Dennis and Sheri A. Mickelson and Elizabeth R. Jessup",
 +keywords = "Community Earth System Model",
 +keywords = "CESM Ensemble Consistency Test",
 +keywords = "statistical consistency",
 +keywords = "code modification as source of variability",
 +keywords = "compiler as source of variability",
 +keywords = "Community Atmosphere Model",
 +keywords = "non-bit-for-bit",
 +keywords = "Fused Multiply-Add"
 } }
melange/papers/spring2017.1485297205.txt.gz · Last modified: 2017/01/24 15:33 by swetha

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