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melange:papers:spring2015 [2015/02/16 13:36]
sanjay |
melange:papers:spring2015 [2016/08/30 12:59]
swetha |
| | @INPROCEEDINGS{6012857, |
| | author={de O Sandes, E. F. and de Melo, A. C. M. A.}, |
| | booktitle={Parallel Distributed Processing Symposium (IPDPS), 2011 IEEE International}, |
| | title={Smith-Waterman Alignment of Huge Sequences with GPU in Linear Space}, |
| | year={2011}, |
| | month=may, |
| | pages={1199-1211}, |
| | keywords={bioinformatics;cellular biophysics;coprocessors;parallel algorithms;GPU;GTX 285 Board;Myers-Miller algorithm;Smith-Waterman alignment;ancestral relationships;bioinformatics;cross-species chromosome alignments;high performance computing platform;linear space complexity;parallel algorithm;species peculiarity identification;Bioinformatics;Computer architecture;Graphics processing unit;Heuristic algorithms;Instruction sets;Mathematical model;Microprocessors}, |
| | doi={10.1109/IPDPS.2011.114}, |
| | ISSN={1530-2075},} |
| | |
| @article{Luporini:2015:COA:2695583.2687415, | @article{Luporini:2015:COA:2695583.2687415, |
| author = {Luporini, Fabio and Varbanescu, Ana Lucia and Rathgeber, Florian and Bercea, Gheorghe-Teodor and Ramanujam, J. and Ham, David A. and Kelly, Paul H. J.}, | author = {Luporini, Fabio and Varbanescu, Ana Lucia and Rathgeber, Florian and Bercea, Gheorghe-Teodor and Ramanujam, J. and Ham, David A. and Kelly, Paul H. J.}, |
| pages={412--425}, | pages={412--425}, |
| year={2013}, | year={2013}, |
| | doi={10.1177/1094342013493939}, |
| publisher={Sage Publications} | publisher={Sage Publications} |
| } | } |
| author={Torrellas, J.}, | author={Torrellas, J.}, |
| booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014}, | booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014}, |
| title={Extreme-scale computer architecture: Energy efficiency from the ground up #x2021;}, | title={Extreme-scale computer architecture: Energy efficiency from the ground up}, |
| year={2014}, | year={2014}, |
| month={March}, | month={March}, |
| pages={1-6}, | pages={1-6}, |
| keywords={microprocessor chips;multiprocessing systems;ILP;Intel processors;architectural innovations;heat dissipation;instruction level parallelism;microprocessor;multicore processor;single-core processors;Clocks;Microarchitecture;Microprocessors;Multicore processing;Program processors;Technological innovation;Transistors;Architectural innovations;Intel microarchitecture;computer architecture;multi-core architecture}, | keywords={microprocessor chips;multiprocessing systems;ILP;Intel processors;architectural innovations;heat dissipation;instruction level parallelism;microprocessor;multicore processor;single-core processors;Clocks;Microarchitecture;Microprocessors;Multicore processing;Program processors;Technological innovation;Transistors;Architectural innovations;Intel microarchitecture;computer architecture;multi-core architecture}, |
| | url={http://dx.doi.org/10.1109/HNICEM.2014.7016212}, |
| doi={10.1109/HNICEM.2014.7016212},} | doi={10.1109/HNICEM.2014.7016212},} |
| |
| pages={113-124}, | pages={113-124}, |
| keywords={application specific integrated circuits;circuit CAD;coprocessors;digital signal processing chips;high level synthesis;integrated circuit design;parallel architectures;DSP chips;PICO-N system;RTL definition;controller local memory;coprocessors;customized VLIW processors;embedded ASIC;embedded nonprogrammable accelerator synthesis;high-level synthesis;initiation interval;interfaces;loop nests;nonprogrammable hardware accelerators;register transfer level;specified throughput;synchronous array;synthesizable VHDL;user application software modification;very-long instruction word processors;Acceleration;Automatic generation control;Control system synthesis;Coprocessors;Hardware;High level synthesis;Process control;Registers;Synchronous generators;VLIW}, | keywords={application specific integrated circuits;circuit CAD;coprocessors;digital signal processing chips;high level synthesis;integrated circuit design;parallel architectures;DSP chips;PICO-N system;RTL definition;controller local memory;coprocessors;customized VLIW processors;embedded ASIC;embedded nonprogrammable accelerator synthesis;high-level synthesis;initiation interval;interfaces;loop nests;nonprogrammable hardware accelerators;register transfer level;specified throughput;synchronous array;synthesizable VHDL;user application software modification;very-long instruction word processors;Acceleration;Automatic generation control;Control system synthesis;Coprocessors;Hardware;High level synthesis;Process control;Registers;Synchronous generators;VLIW}, |
| doi={10.1109/ASAP.2000.862383}, | doi={10.1109/ASAP.2000.862383}, |
| ISSN={2160-0511},} | ISSN={2160-0511},} |
| | |
| | @ARTICLE{595572, |
| | author={Andonov, R. and Rajopadhye, S.}, |
| | journal={Parallel and Distributed Systems, IEEE Transactions on}, |
| | title={Knapsack on VLSI: From algorithm to optimal circuit}, |
| | year={1997}, |
| | month={jun}, |
| | volume={8}, |
| | number={6}, |
| | pages={545-561}, |
| | keywords={VLSI;application specific integrated circuits;logic design;parallel algorithms;systolic arrays;NP-hard problem;application specific VLSI design;correctness preserving transformations;dynamic dependencies;linear systolic array;model of computation;nonlinear discrete optimization;parallel solution;recurrence equations;space-time transformations;systolic arrays;systolic synthesis;unbounded knapsack problem;Circuits;Computational modeling;Control system synthesis;Difference equations;NP-hard problem;Nonlinear equations;Phase change random access memory;Sufficient conditions;Systolic arrays;Very large scale integration}, |
| | doi={10.1109/71.595572}, |
| | ISSN={1045-9219},} |
| | @inproceedings{Hoefler:2015:SBP:2807591.2807644, |
| | author = {Hoefler, Torsten and Belli, Roberto}, |
| | title = {Scientific Benchmarking of Parallel Computing Systems: Twelve Ways to Tell the Masses when Reporting Performance Results}, |
| | booktitle = {Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis}, |
| | series = {SC '15}, |
| | year = {2015}, |
| | isbn = {978-1-4503-3723-6}, |
| | location = {Austin, Texas}, |
| | pages = {73:1--73:12}, |
| | articleno = {73}, |
| | numpages = {12}, |
| | url = {http://doi.acm.org/10.1145/2807591.2807644}, |
| | doi = {10.1145/2807591.2807644}, |
| | acmid = {2807644}, |
| | publisher = {ACM}, |
| | address = {New York, NY, USA}, |
| | keywords = {benchmarking, data analysis, parallel computing, statistics}, |
| | } |
| | |
| | |
| | @inproceedings{Bender:2016:CA:2935764.2935798, |
| | author = {Bender, Michael A. and Demaine, Erik D. and Ebrahimi, Roozbeh and Fineman, Jeremy T. and Johnson, Rob and Lincoln, Andrea and Lynch, Jayson and McCauley, Samuel}, |
| | title = {Cache-Adaptive Analysis}, |
| | booktitle = {Proceedings of the 28th ACM Symposium on Parallelism in Algorithms and Architectures}, |
| | series = {SPAA '16}, |
| | year = {2016}, |
| | isbn = {978-1-4503-4210-0}, |
| | location = {Pacific Grove, California, USA}, |
| | pages = {135--144}, |
| | numpages = {10}, |
| | url = {http://doi.acm.org/10.1145/2935764.2935798}, |
| | doi = {10.1145/2935764.2935798}, |
| | acmid = {2935798}, |
| | publisher = {ACM}, |
| | address = {New York, NY, USA}, |
| | keywords = {cache adaptive, cache oblivious, external memory, memory adaptive, paging algorithms}, |
| | } |
| | |
| | @inproceedings{Bhaskaracharya:2016:SIA:2837614.2837636, |
| | author = {Bhaskaracharya, Somashekaracharya G. and Bondhugula, Uday and Cohen, Albert}, |
| | title = {SMO: An Integrated Approach to Intra-array and Inter-array Storage Optimization}, |
| | booktitle = {Proceedings of the 43rd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages}, |
| | series = {POPL '16}, |
| | year = {2016}, |
| | isbn = {978-1-4503-3549-2}, |
| | location = {St. Petersburg, FL, USA}, |
| | pages = {526--538}, |
| | numpages = {13}, |
| | url = {http://doi.acm.org/10.1145/2837614.2837636}, |
| | doi = {10.1145/2837614.2837636}, |
| | acmid = {2837636}, |
| | publisher = {ACM}, |
| | address = {New York, NY, USA}, |
| | keywords = {Compilers, array contraction, memory optimization, polyhedral framework, storage mapping optimization}, |
| | } |
| | |
| | |
| | @INPROCEEDINGS{7429307, |
| | author={P. Chatarasi and J. Shirako and V. Sarkar}, |
| | booktitle={2015 International Conference on Parallel Architecture and Compilation (PACT)}, |
| | title={Polyhedral Optimizations of Explicitly Parallel Programs}, |
| | year={2015}, |
| | pages={213-226}, |
| | doi={10.1109/PACT.2015.44}, |
| | ISSN={1089-795X}, |
| | month={Oct},} |
| | |
| | |
| | @INPROCEEDINGS{7429326, |
| | author={V. Porpodas and T. M. Jones}, |
| | booktitle={2015 International Conference on Parallel Architecture and Compilation (PACT)}, |
| | title={Throttling Automatic Vectorization: When Less is More}, |
| | year={2015}, |
| | pages={432-444}, |
| | doi={10.1109/PACT.2015.32}, |
| | ISSN={1089-795X}, |
| | month={Oct},} |
| | |
| | |
| |
