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melange:papers:spring2015 [2015/02/12 18:14]
waruna |
melange:papers:spring2015 [2016/08/30 13:00] (current)
swetha |
| | @INPROCEEDINGS{6012857, |
| | author={de O Sandes, E. F. and de Melo, A. C. M. A.}, |
| | booktitle={Parallel Distributed Processing Symposium (IPDPS), 2011 IEEE International}, |
| | title={Smith-Waterman Alignment of Huge Sequences with GPU in Linear Space}, |
| | year={2011}, |
| | month=may, |
| | pages={1199-1211}, |
| | keywords={bioinformatics;cellular biophysics;coprocessors;parallel algorithms;GPU;GTX 285 Board;Myers-Miller algorithm;Smith-Waterman alignment;ancestral relationships;bioinformatics;cross-species chromosome alignments;high performance computing platform;linear space complexity;parallel algorithm;species peculiarity identification;Bioinformatics;Computer architecture;Graphics processing unit;Heuristic algorithms;Instruction sets;Mathematical model;Microprocessors}, |
| | doi={10.1109/IPDPS.2011.114}, |
| | ISSN={1530-2075},} |
| | |
| @article{Luporini:2015:COA:2695583.2687415, | @article{Luporini:2015:COA:2695583.2687415, |
| author = {Luporini, Fabio and Varbanescu, Ana Lucia and Rathgeber, Florian and Bercea, Gheorghe-Teodor and Ramanujam, J. and Ham, David A. and Kelly, Paul H. J.}, | author = {Luporini, Fabio and Varbanescu, Ana Lucia and Rathgeber, Florian and Bercea, Gheorghe-Teodor and Ramanujam, J. and Ham, David A. and Kelly, Paul H. J.}, |
| |
| @article{Elango:2015:URM:2695583.2693656, | @article{Elango:2015:URM:2695583.2693656, |
| author = {Elango, Venmugil and Sedaghati, Naser and Rastello, Fabrice and Pouchet, Louis-No\\"{e}l and Ramanujam, J. and Teodorescu, Radu and Sadayappan, P.}, | author = {Elango, Venmugil and Sedaghati, Naser and Rastello, Fabrice and Pouchet, Louis-Noël and Ramanujam, J. and Teodorescu, Radu and Sadayappan, P.}, |
| title = {On Using the Roofline Model with Lower Bounds on Data Movement}, | title = {On Using the Roofline Model with Lower Bounds on Data Movement}, |
| journal = {ACM Trans. Archit. Code Optim.}, | journal = {ACM Trans. Archit. Code Optim.}, |
| |
| @article{Kong:2015:CFD:2695583.2687652, | @article{Kong:2015:CFD:2695583.2687652, |
| author = {Kong, Martin and Pop, Antoniu and Pouchet, Louis-No\"{e}l and Govindarajan, R. and Cohen, Albert and Sadayappan, P.}, | author = {Kong, Martin and Pop, Antoniu and Pouchet, Louis-Noël and Govindarajan, R. and Cohen, Albert and Sadayappan, P.}, |
| title = {Compiler/Runtime Framework for Dynamic Dataflow Parallelization of Tiled Programs}, | title = {Compiler/Runtime Framework for Dynamic Dataflow Parallelization of Tiled Programs}, |
| journal = {ACM Trans. Archit. Code Optim.}, | journal = {ACM Trans. Archit. Code Optim.}, |
| pages={412--425}, | pages={412--425}, |
| year={2013}, | year={2013}, |
| | doi={10.1177/1094342013493939}, |
| publisher={Sage Publications} | publisher={Sage Publications} |
| } | } |
| |
| @inproceedings{Pouchet:2011:LTC:1926385.1926449, | @inproceedings{Pouchet:2011:LTC:1926385.1926449, |
| author = {Pouchet, Louis-No\"{e}l and Bondhugula, Uday and Bastoul, C{\'e}dric and Cohen, Albert and Ramanujam, J. and Sadayappan, P. and Vasilache, Nicolas}, | author = {Pouchet, Louis-Noël and Bondhugula, Uday and Bastoul, Cédric and Cohen, Albert and Ramanujam, J. and Sadayappan, P. and Vasilache, Nicolas}, |
| title = {Loop Transformations: Convexity, Pruning and Optimization}, | title = {Loop Transformations: Convexity, Pruning and Optimization}, |
| booktitle = {Proceedings of the 38th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages}, | booktitle = {Proceedings of the 38th Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages}, |
| url={http://dx.doi.org/10.1007/978-3-642-28652-0_6}, | url={http://dx.doi.org/10.1007/978-3-642-28652-0_6}, |
| publisher={Springer Berlin Heidelberg}, | publisher={Springer Berlin Heidelberg}, |
| author={Shirako, Jun and Sharma, Kamal and Fauzia, Naznin and Pouchet, Louis-Noël and Ramanujam, J. and Sadayappan, P. and Sarkar, Vivek}, | author={Shirako, Jun and Sharma, Kamal and Fauzia, Naznin and Pouchet, Louis-Noël and Ramanujam, J. and Sadayappan, P. and Sarkar, Vivek}, |
| pages={101-121}, | pages={101-121}, |
| language={English} | language={English} |
| |
| @inproceedings{Henretty:2013:SCS:2464996.2467268, | @inproceedings{Henretty:2013:SCS:2464996.2467268, |
| author = {Henretty, Tom and Veras, Richard and Franchetti, Franz and Pouchet, Louis-No\"{e}l and Ramanujam, J. and Sadayappan, P.}, | author = {Henretty, Tom and Veras, Richard and Franchetti, Franz and Pouchet, Louis-Noël and Ramanujam, J. and Sadayappan, P.}, |
| title = {A Stencil Compiler for Short-vector SIMD Architectures}, | title = {A Stencil Compiler for Short-vector SIMD Architectures}, |
| booktitle = {Proceedings of the 27th International ACM Conference on International Conference on Supercomputing}, | booktitle = {Proceedings of the 27th International ACM Conference on International Conference on Supercomputing}, |
| author = {Paul, Somnath and Karam, Robert and Bhunia, Swarup and Puri, Ruchir}, | author = {Paul, Somnath and Karam, Robert and Bhunia, Swarup and Puri, Ruchir}, |
| title = {Energy-efficient Hardware Acceleration Through Computing in the Memory}, | title = {Energy-efficient Hardware Acceleration Through Computing in the Memory}, |
| booktitle = {Proceedings of the Conference on Design, Automation \& Test in Europe}, | booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe}, |
| series = {DATE '14}, | series = {DATE '14}, |
| year = {2014}, | year = {2014}, |
| author={Torrellas, J.}, | author={Torrellas, J.}, |
| booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014}, | booktitle={Design, Automation and Test in Europe Conference and Exhibition (DATE), 2014}, |
| title={Extreme-scale computer architecture: Energy efficiency from the ground up #x2021;}, | title={Extreme-scale computer architecture: Energy efficiency from the ground up}, |
| year={2014}, | year={2014}, |
| month={March}, | month={March}, |
| pages={1-6}, | pages={1-6}, |
| keywords={microprocessor chips;multiprocessing systems;ILP;Intel processors;architectural innovations;heat dissipation;instruction level parallelism;microprocessor;multicore processor;single-core processors;Clocks;Microarchitecture;Microprocessors;Multicore processing;Program processors;Technological innovation;Transistors;Architectural innovations;Intel microarchitecture;computer architecture;multi-core architecture}, | keywords={microprocessor chips;multiprocessing systems;ILP;Intel processors;architectural innovations;heat dissipation;instruction level parallelism;microprocessor;multicore processor;single-core processors;Clocks;Microarchitecture;Microprocessors;Multicore processing;Program processors;Technological innovation;Transistors;Architectural innovations;Intel microarchitecture;computer architecture;multi-core architecture}, |
| | url={http://dx.doi.org/10.1109/HNICEM.2014.7016212}, |
| doi={10.1109/HNICEM.2014.7016212},} | doi={10.1109/HNICEM.2014.7016212},} |
| |
| pages={113-124}, | pages={113-124}, |
| keywords={application specific integrated circuits;circuit CAD;coprocessors;digital signal processing chips;high level synthesis;integrated circuit design;parallel architectures;DSP chips;PICO-N system;RTL definition;controller local memory;coprocessors;customized VLIW processors;embedded ASIC;embedded nonprogrammable accelerator synthesis;high-level synthesis;initiation interval;interfaces;loop nests;nonprogrammable hardware accelerators;register transfer level;specified throughput;synchronous array;synthesizable VHDL;user application software modification;very-long instruction word processors;Acceleration;Automatic generation control;Control system synthesis;Coprocessors;Hardware;High level synthesis;Process control;Registers;Synchronous generators;VLIW}, | keywords={application specific integrated circuits;circuit CAD;coprocessors;digital signal processing chips;high level synthesis;integrated circuit design;parallel architectures;DSP chips;PICO-N system;RTL definition;controller local memory;coprocessors;customized VLIW processors;embedded ASIC;embedded nonprogrammable accelerator synthesis;high-level synthesis;initiation interval;interfaces;loop nests;nonprogrammable hardware accelerators;register transfer level;specified throughput;synchronous array;synthesizable VHDL;user application software modification;very-long instruction word processors;Acceleration;Automatic generation control;Control system synthesis;Coprocessors;Hardware;High level synthesis;Process control;Registers;Synchronous generators;VLIW}, |
| doi={10.1109/ASAP.2000.862383}, | doi={10.1109/ASAP.2000.862383}, |
| ISSN={2160-0511},} | ISSN={2160-0511},} |
| | |
| | @ARTICLE{595572, |
| | author={Andonov, R. and Rajopadhye, S.}, |
| | journal={Parallel and Distributed Systems, IEEE Transactions on}, |
| | title={Knapsack on VLSI: From algorithm to optimal circuit}, |
| | year={1997}, |
| | month={jun}, |
| | volume={8}, |
| | number={6}, |
| | pages={545-561}, |
| | keywords={VLSI;application specific integrated circuits;logic design;parallel algorithms;systolic arrays;NP-hard problem;application specific VLSI design;correctness preserving transformations;dynamic dependencies;linear systolic array;model of computation;nonlinear discrete optimization;parallel solution;recurrence equations;space-time transformations;systolic arrays;systolic synthesis;unbounded knapsack problem;Circuits;Computational modeling;Control system synthesis;Difference equations;NP-hard problem;Nonlinear equations;Phase change random access memory;Sufficient conditions;Systolic arrays;Very large scale integration}, |
| | doi={10.1109/71.595572}, |
| | ISSN={1045-9219},} |
| | |
| | |
| |
