User Tools

Site Tools


This is an old revision of the document!

Schedule : Spring 2018

This is the tentative schedule of Mélange group for the Spring 2018 semester.

Meet time & Place : Wednesdays 10:00 AM - 11:00 AM @ CSB 305

0 01/17/2018 SPX proposal : PARRIC Sanjay Rajopadhye
1 01/24/2018 Execution time models Fabrice Rastello
2 01/31/2018 TBD
3 02/07/2018 TBD
4 02/14/2018 TBD
5 02/21/2018 TBD
6 02/28/2018 TBD
7 03/07/2018 TBD
8 03/14/2018 SPRING BREAK
9 03/21/2018 TBD
10 03/28/2018 TBD
11 04/04/2018 TBD
12 04/11/2018 TBD
13 04/18/2018 TBD
14 04/25/2018 TBD
15 05/02/2018 TBD
16 05/09/2018 TBD

Reading Pool


  • Johannes Doerfert, Tobias Grosser, Sebastian Hack, Optimistic Loop Optimization, 2017
  • Chris Cummins, Pavlos Petoumenos, Zheng Wang, Hugh Leather, Synthesizing benchmarks for predictive modeling, 2017
  • Wenlei Bao, Changwan Hong, Sudheer Chunduri, Sriram Krishnamoorthy, Louis-Noel Pouchet, Fabrice Rastello, P. Sadayappan, Static and Dynamic Frequency Scaling on Multicore CPUs, 2016
  • William Ogilvie, Pavlos Petoumenos, Zheng Wang, Hugh Leather, Minimizing the cost of iterative compilation with active learning, 2016
  • Daniel J. Milroy, Allison H. Baker, Dorit M. Hammerling, John M. Dennis, Sheri A. Mickelson, Elizabeth R. Jessup, Towards Characterizing the Variability of Statistically Consistent Community Earth System Model Simulations, 2016
  • Audrunas Gruslys, R{ '{e}}mi Munos, Ivo Danihelka, Marc Lanctot, Alex Graves, Memory-Efficient Backpropagation Through Time, 2016
  • U. Bondhugula, V. Bandishti, I. Pananilath, Diamond Tiling: Tiling Techniques to Maximize Parallelism for Stencil Computations, 2016
  • T. Nowatzki, J. Menon, C. H. Ho, K. Sankaralingam, Architectural Simulators Considered Harmful, 2015
  • J. D. Garvey, T. S. Abdelrahman, Automatic Performance Tuning of Stencil Computations on GPUs, 2015
  • Eric Chung Kalin Ovtcharov, Accelerating Deep Convolutional Neural Networks Using Specialized Hardware, 2015
  • Protonu Basu, Mary Hall, Samuel Williams, Brian Van Straalen, Leonid Oliker, Phillip Colella, Compiler-Directed Transformation for Higher-Order Stencils, 2015
  • Andrew Putnam, Adrian M. Caulfield, Eric S. Chung, Derek Chiou, Kypros Constantinides, John Demme, Hadi Esmaeilzadeh, Jeremy Fowers, Gopi Prashanth Gopal, Jan Gray, Michael Haselman, Scott Hauck, Stephen Heil, Amir Hormati, Joo-Young Kim, Sitaram Lanka, James Larus, Eric Peterson, Simon Pope, Aaron Smith, Jason Thong, Phillip Yi Xiao, Doug Burger, A Reconfigurable Fabric for Accelerating Large-scale Datacenter Services, 2014
  • Sharan Chetlur, Cliff Woolley, Philippe Vandermersch, Jonathan Cohen, John Tran, Bryan Catanzaro, Evan Shelhamer, cuDNN: Efficient Primitives for Deep Learning, 2014
  • Martin Kong, Richard Veras, Kevin Stock, Franz Franchetti, Louis-No “{e}l Pouchet, P. Sadayappan, When Polyhedral Transformations Meet SIMD Code Generation, 2013
  • Louis-Noel Pouchet, Peng Zhang, P. Sadayappan, Jason Cong, Polyhedral-based Data Reuse Optimization for Configurable Computing, 2013
  • Vinayaka Bandishti, Irshad Pananilath, Uday Bondhugula, Tiling Stencil Computations to Maximize Parallelism, 2012
  • A. Pedram, A. Gerstlauer, R. A. v. d. Geijn, A high-performance, low-power linear algebra core, 2011
  • Henry Wong, Vaughn Betz, Jonathan Rose, Comparing FPGA vs. Custom Cmos and the Impact on Processor Microarchitecture, 2011
  • J. Ramanujam Sanket Tavarageri, P. Sadayappan, Parametric Tiling of Affine Loop Nests, 2010
  • Andrew R. Putnam, Dave Bennett, Eric Dellinger, Jeff Mason, Prasanna Sundararajan, CHiMPS: A High-level Compilation Flow for Hybrid CPU-FPGA Architectures, 2008
  • Steven J. Deitz, Bradford L. Chamberlain, Lawrence Snyder, Eliminating Redundancies in Sum-of-product Array Computations, 2001
  • J. Cong, Yuzheng Ding, FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs, 1994
melange/schedule/spring2017.1516131391.txt.gz · Last modified: 2018/01/16 12:36 by prerana