CS/EE 560: Reconfigurable Computing, Spring 2008
Class meets: Tu-Th 15:30-16:45; USC 310B
Be sure to watch this space. Late breaking info will be
posted here, rather than sent by email.
Also be sure to frequently check
the Class Schedule
- [We mar 12 9:00 am:] Here's
the midterm exam.
- [Su 24 Feb 3:30 pm:] HW 3 (due next tuesday) has been posted in
the Class Schedule.
- [Th 21 Feb 5:30 pm:] For scribes, I've posted a LyX template that you are strongly encouraged
- [Fri 15 Feb 11:30 am:] Thanks to Alan and Andy, the notes on
executing equations have beeen
- [Th 7 Feb 2:15 am:] I have posted
a reading assignment for this weekend.
Please prepare your critique for discusssion next Tuesday. I will build on
it, and we will move on to techniques for automatic derivation os systolic
arrays. It should take you about 3 hours (my estimate, I'll take a poll in
class on Tuesday). Also, PCP 2 has been postponed to Thursday, Feb 14).
- [Th 7 Feb 11:15 am:] We are all past PCP 1 (choose your project).
I would appreciate if for my record, you send me an email confirming this
(some of you have already done this).
- [Th 7 Feb 11:00 am:] Homework 2 has been posted (the
annnouncement is slightly different from what I handed out (but you don't
have to print it out to note the differences) on the following points.
- I have given a few more details about what to draw in Problem 2.
- I have noted the points for each problem.
- I have given a few more instructions (e.g., memoized or not) to the
kind of code I'd like you to write for Problems 3 and 4.
- I have asked an additional small question in Problem 4.
- [Sa 1 Feb 9:30 am:] The list of
projects has been posted.
- [Fr 25 Jan 8:30 pm:] HW 0 has been posted on
the Class Schedule.
- [Th 24 Jan 2:50 pm:] The notes have been slightly updated (a
couple of typos have been corrected, and I changed the font size). If
you've already printed out a copy, please don't bother (figuring out the
typos will teach you more, and also you'll feel better for saving a few
- [Tu 22 Jan 6:15 pm:] The notes have been posted in the class
schedule (Notes 1).
- Here are details about the class
projects including a tentative schedule.
- The Tentative Class Schedule is another page
that will evolve and grow as we go along. You should refer to it frequently
since all homework/lab assignments and readings will be posted there.
- Previous announcements
This course is the graduate level complement to
(Embedded Systems) in a new
curriculum in High Level Programming for High
Performance Embedded Computing Systems, sponsored by NSF and CSU.
The original focus of CS560 was on fine grain parallel architectures and the
use of high level models, languages tools and abstractions, using CS/ECE 460
as a prerequisite. This focus has been enlarged as described below, to allow
CS475 as an alternative prerequisite.
In this class you will learn the foundations of fine grain parallelism
covering (i) the polyhedral model and (ii) stream based
and data parallel models. Fine grain parallelism may be studied from
an architectural view or as an abstraction for general purpose parallel
programming. The first view is appropriate for students with prior experience
with FPGAs (i.e., with the CS 460 prerequisite). The second view is relevant
to students with a general purpose parallel programming training (e.g., the
Project: You will transform your understanding of
the foundations by demonstrating in your term project, highly tuned
parallel implementations of the compute intensive kernels of selected
applications on a specific platform of your choice.
Depending on your background and aptitude, you may implement your designs on
either (i) special purpose hardware on FPGA based platforms; or (ii) parallel
programs for the IBM Cell. Specifically, the following platforms will be
Here are some more details about the project
including a tentative schedule.
- The Spartan 3 based Digilent boards used in CS/ECE 460.
The ADM-XRC-II a
high-performance PMC (PCI Mezzanine Card)
from Alpha Data that we have
available for use in the department's Embedded Systems Lab. It is much
more powerful than the boards used in CS460, and capable of delivering
sustained high performance (e.g., 20 GOPS on some applications that we
have run). Please note that you will be expected to take significant
initiative in working with the available tools and libraries. You will
also have the option to implement/simulate your fine-grain parallel
architectures in VHDL and ModelSim.
- A Sony Playstation 3 (about 150 GFLOP single precision peak
performance). We have been able to achieve over 100 GFLOPs sustained on
certain applications, and this is the target that we will aim for.
Class Topics: The first part of the course will
cover a class of highly parallel architectures called systolic arrays
that are used for the compute/data intensive parts of many
applications. Next, we will see how to systematically design such
architectures from high level equational specifications (programs) using the
polyhedral model. We will then study tiling and its relationship to systolic
architectures as well as to general purpose parallel programming.
The second part will cover stream based and data parallel
programming models, and their compilation to hardware. Specifically, we will
study an important model of streams called Kahn process networks, its
relation to the SAC language developed at CSU, and the automatic compilation
of SAC programs to reconfigurable coprocessors.