Back to BMAC Page
Warp Processors, Roman L. Lysecky
Hardware/software partitioning, which partitions an application among
software running on a microprocessor and hardware co-processors in
on-chip configurable logic, has been shown to provide tremendous
speedups and energy savings for many applications. However, such
partitioning has only been implemented as a desktop computer-aided
design (CAD) tool that frequently requires the designers expertise to
achieve such results. Meanwhile, dynamic software optimization methods
have shown the usefulness and feasibility of runtime program
optimization, but such optimizations do not achieve as much as
partitioning. Recently, researchers have shown that desktop
hardware/software partitioning could be performed starting from binaries
rather than from high-level code, with competitive performance and
energy results. Such partitioning opens the door to dynamic
hardware/software partitioning, in which an executing binary is
dynamically and transparently optimized by moving software kernels to
configurable logic - a process called warp processing, since performance
and energy are automatically warped during software execution. In this
seminar, we present our warp processor architecture, focusing on the
development of our Warp Configurable Logic Architecture (WCLA) and lean
Just-in-time (JIT) compilation tools. We examine the requirements of our
configurable logic architecture and JIT compilation tools, and
demonstrate by developing our WCLA and JIT compiler simultaneously, we
are able to create lean versions of technology mapping, placement, and
routing tools requiring an order of magnitude less execution time and
memory requirements compared with their desktop-based tool counterparts
while producing acceptable quality hardware circuits. Finally, we
highlight the overall performance and energy benefits of warp processors
for several embedded systems benchmarks.
Back to BMAC Page