Journal and Book Chapter Publications
- Optimizing Coherence Traffic in Manycore Processors Using Closed-Form Caching/Home Agent Mappings. (2021, IEEE Access)
- R-Hero: A Software Repair Bot based on Continual Learning. (2020, IEEE Software)
- Self-Supervised Learning for Multi-goal Grid World: Comparing Leela and Deep Q Network. (2020, Proceedings of Machine Learning Research)
- SequenceR: Sequence-to-Sequence Learning for End-to-End Program Repair (2019, IEEE TSE)
- Biomedical Image Analytics: Automated Lung Cancer Diagnosis (2019, Deep Learning through Sparse and Low-Rank Modeling, Academic Press)
- Reducing power in AMD processor core with RTL clock gating analysis (2013, EETimes)
- An 11.8-in Flat Panel Display Monitor (1995, HP Journal)
Conference and Peer-reviewed Workshop Publications
- SEQUENCER: Sequence-to-Sequence Learning for End-to-End Program Repair (2020, ICSE)
- Synthetic Lung Nodule 3D Image Generation Using Autoencoders (2019, IJCNN)
- Synthetic Lung Nodule 3D Image Generation Using Autoencoders (2018, Workshop on Biomedical Informatics with Optimization and Machine Learning, IJCAI)
- A Smart Synchronizer - Pragmatic way to cross asynchronous clock domains (2011, DVCON)
- AMD Geode GX2 x86 System-on-Chip (2004, Embedded Processor Forum)
Selected Talks, Presentations and Other Publications
- Neural Transfer Learning for Repairing Security Vulnerabilities in C Code (2021, arXiv)
- Equivalence of Dataflow Graphs via Rewrite Rules Using a Graph-to-Sequence Neural Model (2020, arXiv)
- Interviewed by Seth Colaner for article: The persistent humanity in AI and cybersecurity (2020, VentureBeat magazine)
- Using Sequence-to-Sequence Learning for Repairing C Vulnerabilities (2019, arXiv)
- Artificial Intelligence Techniques for Security Vulnerability Prevention (2019, arXiv)
- Repairnator overview and machine learning for program repair (2018, invited talk at University College London)
- Synthetic Lung Nodule 3D Image Generation Using Autoencoders (2018, invited talk at KTH, Stockholm, Sweden in the Jonasson seminar series)
- Ethical Systems and Artificial Superintelligence (2018, invited talk at DaVinci Institute available on YouTube)
- AI Race Safety through Agile Risk Management (2018, in collaboration with FC-MLMI team)
- Implementing an Efficient RTL Clock Gating Analysis Flow at AMD (2013, presented in Calypto booth at Design Automation Conference)
- The Innovator's Dilemma: Managing the Invention process (at Professional Learning Institute day at CSU)
- Clock distribution for low power and minimal skew on modern System-On-Chip designs (2007, Invited talk at VEDA IIT, Hyderabad, India)
Selections from AMD internal work:
- Sole author for the Jaguar core clock/reset/power management specification (the CPU used in PS4 and Xbox One)
- Lead author for the Zen multicore clock/reset/power management specification (the CPU used in Ryzen and EPYC)
- Lead Twiki author and international conference coordinator for AMD-wide clock domain crossing techniques
- Presented "Design for Power Methodologies" to engineering leads at Technical Leadership Forum
Patents
- Clock adjustment for voltage droop
Issued May 5, 2020 United States Patent Number 10642336 - Asynchronous buffer with pointer offsets
Issued March 17, 2020 United States Patent Number 10592442 - Adaptive oscillator for clock generation
Issued August 13, 2019 United States Patent Number 10382014 - Clock divider device and methods thereof
Issued May 28, 2019 United States Patent Number 10303200 - Managing frequency changes of clock signals across different clock domains
Issued Jan 1, 2019 United States Patent Number 10168731 - Propagation simulation buffer for clock domain crossing
Issued Apr 11, 2017. United States Patent Number 9621143 - Power Management for Multiple Compute Units
Issued Jun 7, 2016. United States Patent Number 9360906 - Power management of multiple compute units sharing a cache
Issued May 26, 2015. United States Patent Number 9043628 - Debug state machines and methods of their operation
Issued May 19, 2015. United States Patent Number 9037911 - Safe reset configuration of fuses and flops
Issued Nov 11, 2014. United States Patent Number 8884668 - State machine for low-noise clocking of high frequency clock
Issued Nov 11, 2014. United States Patent Number 8884663 - Debug state machine cross triggering
Issued Mar 25, 2014. United States Patent Number 8683265 - Clock domain crossing buffer
Issued Nov 12, 2013. United States Patent Number 8584067 - Digital frequency synthesizer device and method thereof
Issued Nov 5, 2013. United States Patent Number 8575972 - Debug state machine and processor including the same
Issued Oct 22, 2013. United States Patent Number 8566645 - Efficient branch trace messaging with hardware debug features
Issued Jan 4, 2011. United States Patent Number 7865879 - Method of configuring a system and system therefor [related to scan test and security]
Issued Apr 14, 2009. United States Patent Number 7519883 - Memory access request arbitration
Issued Sep 16, 2008. United States Patent Number 7426621 - Device having an interface and method thereof [for DDR strobe positioning]
Issued Mar 6, 2007. United States Patent Number 7187598 - DDR on-the-fly synchronization
Issued Feb 13, 2007. United States Patent Number 7177379 - Apparatus and method for initiating a sleep state in a system on a chip device
Issued May 2, 2006. United States Patent Number 7039819 - Precision bypass clock for high speed testing of a data processor
Issued Feb 28, 2006. United States Patent Number 7007188 - High speed asynchronous bus for an integrated circuit
Issued Sep 21, 2004. United States Patent Number 6795882 - High speed linear feedback shift register
Issued Nov 25, 2003. United States Patent Number 6654439 - Digital image scanner with compensation for misalignment of photosensor array segments
Issued Apr 29, 2003. United States Patent Number 6556315 - Computer graphics system having per pixel fog blending
Issued Aug 20, 2002. United States Patent Number 6437781 - Phase locked loop clock divider utilizing a high speed programmable linear feedback shift register
Issued Jul 23, 2002. United States Patent Number 6424691 - Constant current voltage restoration
Issued Sep 3, 1996. United States Patent Number 5552783 - Dot clock generation with minimal clock skew
Issued Jul 23, 1996. United States Patent Number 5539473 - Computer graphics system and method for capping volume enclosing polyhedron after sectioning
Issued Feb 20, 1996. United States Patent Number 5493653 - High speed sync separation system and method
Issued Feb 6, 1996. United States Patent Number 5489946 - Frame rate conversion with asynchronous pixel clocks
Issued Aug 29, 1995. United States Patent Number 5446496 - Computer system and method for interference checking of polyhedra using capping polygons
Issued Aug 22, 1995. United States Patent Number 5444838