CS470: Computer Architecture
[Spring 2017]

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Course Objectives:

Computers today range from high performance machines to smartphones and embedded processors in appliances. They crunch numbers, drive high definition displays as well as run everyday applications. The course covers: How to build a functional unit using lower level components in an optimal way (cost/power/performance). Combinational and sequential blocks using gates and storage elements. Processor specification using ISA Implementing high-level language constructs using machine/assembly language. Exploiting potential parallelism to achieve high performance. Memory hierarchy to achieve a large address space with a low cost with fast access. How is technology advancing? What to expect in near future? See Outline


a grade of 'C' or better in CS 370 (System Architecture and Software).

Quad-core prcessor

David A. Patterson & John L. Hennessy, Computer Organization & Design: The Hardware/Software Interface, 5th ed., Morgan Kaufmann Publishers, Inc. Some material will be taken from recent publications and other sources.


There will be about six homework and programming assignments. Some assignments will include use of simulation at the logic level and some will use a machine/assembly level simulator.


There will be one midterm and a comprehensive Final Exam.


In addition there will be about 12 quizzes, mostly on-line on Canvas, but some may in the class, some of which may be unannounced.

Term project in Computer Architecture:

Proposal (1-page): 3/21/2017, progress report: 4/11/2017, final report: 5/4/2017. A short presentation powerpoint presentation will be required (Slides needd 4/27/2017).

Lecture Coordinates
BHSCI 107 MWF (3:00 PM -3:50 PM)


The weights associated with different elements of the course are listed below.

Course Element Dates Weight
Midterm Fri Mar 10 20%
Final Mon May 8 2017 25%
Homeworks & Programs as assigned about 18%
Quizes in-class or online about 18%
Project See above 15%
Class participation 4%
Total 100%

  • Assignments are due on the due date at the start of class, or by the time specified if electronic submission by CANVAS is required.

  • You may turn assignments in up to 24 hours late for a 20% penalty. No credit will be given after that. In some case, there may be no late period.

  • If you will not be able to take an exam or make an assignment deadline due to an exceptional reason that can be documented, you must request the instructor in advance for possible alternative arrangements.

  • Students must read the CS Department Student Information Sheet.

Instructor Graduate Teaching Assistants
  Yashwant K. Malaiya
Office: Room 356, CS Building
Office Hours: W 4:10-5:00 PM, F 10:10-11:00 AM
E-mail: malaiya {aT} cs.colostate.edu
(with the obvious change)
Tel: 970.491.7031
  Athith Amarnath
E-mail: athith.amarnath {aT} colostate.edu
Office Hours in CSB 120:
Mondays 4:00-6:00PM, Fridays 11:00AM-1:00PM
Topic Outline:
  1. Review of logic design basics
    • Gates, boolean algebra and truth tables
    • Combinational logic and functional blocks (MUX, decoders, Adders, PLAs)
    • Flip-flops, registers and memories
    • Timing analysis
    • Finite state machines
    • Use of software packages for simulation
  2. Computer Performance and Trends
    • Measuring performance; Metrics
    • Benchmarks
    • Trends in density, performance and cost
  3. Assembly language programming
    • Operations; Operands
    • Instruction formats and Addressing Modes
    • Decision-making
    • Procedure/function calls; Stack
    • Arrays; Pointers
    • RISC and CISC processors
  4. Computer Arithmetic
    • Numbers and codes
    • Binary arithmetic and hardware implementation
    • Floating-point numbers
    • Implementation of Multiplication and division hardware
  5. Central Processing Unit
    • Structure; Datapaths
    • Control unit
    • Instruction execution
    • FSM and microprogrammed control*
  6. Parallelism for enhanced performance
    • Pipelined Datapaths
    • Data Hazards; Forwarding; Stalls
    • Branch Hazards
    • Exceptions*
    • Multiple Issue
  7. Memory Hierarchy
    • Cache Implementations
    • Cache Performance
    • Memory Hierarchy
  8. Storage and IO
    • Buses and hubs
    • RAID
  9. Multiple processor systems
    • SIMD Multimedia Extensions*
    • Multicore*

Department of Computer Science, Colorado State University,
Fort Collins, CO 80523 USA
© 2017 Colorado State University